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19-44 Vol. 3
ARCHITECTURE COMPATIBILITY
Earlier IA-32 processors (such as the Intel486 and Pentium processors) used the
KEN# (cache enable) pin and external logic to maintain an external memory map and
signal cacheable accesses to the processor. The MTRR mechanism simplifies hard-
ware designs by eliminating the KEN# pin and the external logic required to drive it.
See Chapter 9, “Processor Management and Initialization,” and Appendix B, “Model-
Specific Registers (MSRs),” for more information on the MTRRs.
19.37.4 Machine-Check Exception and Architecture
The Pentium processor introduced a new exception called the machine-check excep-
tion (#MC, interrupt 18). This exception is used to detect hardware-related errors,
such as a parity error on a read cycle.
The P6 family processors extend the types of errors that can be detected and that
generate a machine-check exception. It also provides a new machine-check architec
-
ture for recording information about a machine-check error and provides extended
recovery capability.
The machine-check architecture provides several banks of reporting registers for
recording machine-check errors. Each bank of registers is associated with a specific
hardware unit in the processor. The primary focus of the machine checks is on bus
and interconnect operations; however, checks are also made of translation lookaside
buffer (TLB) and cache operations.
The machine-check architecture can correct some errors automatically and allow for
reliable restart of instruction execution. It also collects sufficient information for soft-
ware to use in correcting other machine errors not corrected by hardware.
See Chapter 15, “Machine-Check Architecture,” for more information on the
machine-check exception and the machine-check architecture.
19.37.5 Performance-Monitoring Counters
The P6 family and Pentium processors provide two performance-monitoring counters
for use in monitoring internal hardware operations. The number of performance
monitoring counters and associated programming interfaces may be implementation
specific for Pentium 4 processors, Pentium M processors. Later processors may have
implemented these as part of an architectural performance monitoring feature. The
architectural and non-architectural performance monitoring interfaces for different
processor families are described in
Chapter 30, “Performance Monitoring,”. Appendix
A, “Performance-Monitoring Events,” lists all the events that can be counted for
architectural performance monitoring events and non-architectural events. The
counters are set up, started, and stopped using two MSRs and the RDMSR and
WRMSR instructions. For the P6 family processors, the current count for a particular
counter can be read using the new RDPMC instruction.