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8-40 Vol. 3
MULTIPLE-PROCESSOR MANAGEMENT
• Debug registers (DR0, DR1, DR2, DR3, DR6, DR7) and the debug control MSRs
• Machine check global status (IA32_MCG_STATUS) and machine check capability
(IA32_MCG_CAP) MSRs
• Thermal clock modulation and ACPI Power management control MSRs
• Time stamp counter MSRs
• Most of the other MSR registers, including the page attribute table (PAT). See the
exceptions below.
• Local APIC registers.
• Additional general purpose registers (R8-R15), XMM registers (XMM8-XMM15),
control register, IA32_EFER on Intel 64 processors.
The following features are shared by logical processors:
• Memory type range registers (MTRRs)
Whether the following features are shared or duplicated is implementation-specific:
• IA32_MISC_ENABLE MSR (MSR address 1A0H)
• Machine check architecture (MCA) MSRs (except for the IA32_MCG_STATUS and
IA32_MCG_CAP MSRs)
• Performance monitoring control and counter MSRs
8.7.2 APIC Functionality
When a processor supporting Intel Hyper-Threading Technology support is initialized,
each logical processor is assigned a local APIC ID (see Table 10-1). The local APIC ID
serves as an ID for the logical processor and is stored in the logical processor’s APIC
ID register. If two or more processors supporting Intel Hyper-Threading Technology
are present in a dual processor (DP) or MP system, each logical processor on the
system bus is assigned a unique local APIC ID (see
Section 8.9.3, “Hierarchical ID of
Logical Processors in an MP System”).
Software communicates with local processors using the APIC’s interprocessor inter-
rupt (IPI) messaging facility. Setup and programming for APICs is identical in proces-
sors that support and do not support Intel Hyper-Threading Technology. See Chapter
10, “Advanced Programmable Interrupt Controller (APIC),” for a detailed discussion.
8.7.3 Memory Type Range Registers (MTRR)
MTRRs in a processor supporting Intel Hyper-Threading Technology are shared by
logical processors. When one logical processor updates the setting of the MTRRs,
settings are automatically shared with the other logical processors in the same phys
-
ical package.
The architectures require that all MP systems based on Intel 64 and IA-32 processors
(this includes logical processors) must use an identical MTRR memory map. This