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8-48 Vol. 3
MULTIPLE-PROCESSOR MANAGEMENT
provided for each logical processors (see Section 8.7, “Intel
®
Hyper-Threading Tech-
nology Architecture,” and Section 8.8, “Multi-Core Architecture”).
From a software programming perspective, control transfer of processor operation is
managed at the granularity of logical processor (operating systems dispatch a
runnable task by allocating an available logical processor on the platform). To
manage the topology of shared resources in a multi-threading environment, it may
be useful for software to understand and manage resources that are shared by more
than one logical processors.
8.9.1 Hierarchical Mapping of Shared Resources
The APIC_ID value associated with each logical processor in a multi-processor
system is unique (see Section 8.6, “Detecting Hardware Multi-Threading Support and
Topology”). This 8-bit or 32-bit value can be decomposed into sub-fields, where each
sub-field corresponds a hierarchical level of the topological mapping of hardware
resources.
The decomposition of an APIC_ID may consist of several sub fields representing the
topology within a physical processor package, the higher-order bits of an APIC ID
may also be used by cluster vendors to represent the topology of cluster nodes of
each coherent multiprocessor systems. If the processor does not support CPUID leaf
0BH, the 8-bit initial APIC ID can represent 4 levels of hierarchy:
• Cluster — Some multi-threading environments consists of multiple clusters of
multi-processor systems. The CLUSTER_ID sub-field is usually supported by
vendor firmware to distinguish different clusters. For non-clustered systems,
CLUSTER_ID is usually 0 and system topology is reduced to three levels of
hierarchy.
• Package — A multi-processor system consists of two or more sockets, each
mates with a physical processor package. The PACKAGE_ID sub-field distin
-
guishes different physical packages within a cluster.
• Core — A physical processor package consists of one or more processor cores.
The CORE_ID sub-field distinguishes processor cores in a package. For a single-
core processor, the width of this bit field is 0.
• SMT — A processor core provides one or more logical processors sharing
execution resources. The SMT_ID sub-field distinguishes logical processors in a
core. The width of this bit field is non-zero if a processor core provides more than
one logical processors.
SMT and CORE sub-fields are bit-wise contiguous in the APIC_ID field (see
Figure 8-5).