Filter
Top Products
10-64 Vol. 3
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
10.11 APIC BUS MESSAGE PASSING MECHANISM AND
PROTOCOL (P6 FAMILY, PENTIUM PROCESSORS)
The Pentium 4 and Intel Xeon processors pass messages among the local and I/O
APICs on the system bus, using the system bus message passing mechanism and
protocol.
The P6 family and Pentium processors, pass messages among the local and I/O
APICs on the serial APIC bus, as follows. Because only one message can be sent at a
time on the APIC bus, the I/O APIC and local APICs employ a “rotating priority” arbi
-
tration protocol to gain permission to send a message on the APIC bus. One or more
APICs may start sending their messages simultaneously. At the beginning of every
message, each APIC presents the type of the message it is sending and its current
arbitration priority on the APIC bus. This information is used for arbitration. After
each arbitration cycle (within an arbitration round), only the potential winners keep
driving the bus. By the time all arbitration cycles are completed, there will be only
one APIC left driving the bus. Once a winner is selected, it is granted exclusive use of
the bus, and will continue driving the bus to send its actual message.
After each successfully transmitted message, all APICs increase their arbitration
priority by 1. The previous winner (that is, the one that has just successfully trans
-
mitted its message) assumes a priority of 0 (lowest). An agent whose arbitration
priority was 15 (highest) during arbitration, but did not send a message, adopts the
previous winner’s arbitration priority, increments by 1.
Note that the arbitration protocol described above is slightly different if one of the
APICs issues a special End-Of-Interrupt (EOI). This high-priority message is granted
Figure 10-31. Spurious-Interrupt Vector Register (SVR)
31
0
Reserved
7
Focus Processor Checking
1
APIC Software Enable/Disable
8910
0: APIC Disabled
1: APIC Enabled
Spurious Vector
2
Address: FEE0 00F0H
Value after reset: 0000 00FFH
0: Enabled
1: Disabled
2. For the P6 family and Pentium processors, bits 0 through 3
of the spurious vector are hardwired to 1.
1. Not supported in Pentium 4 and Intel Xeon processors.