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Vol. 3 16-39
DEBUGGING, PROFILING BRANCHES AND TIME-STAMP COUNTER
LBR MSR pair) that contains the most recent (last) branch record placed on the stack.
Prior to placing a new branch record on the stack, the TOS is incremented by 1. When
the TOS pointer reaches it maximum value, it wraps around to 0. See Table 16-10
and Figure 16-12.
Table 16-10. LBR MSR Stack Size and TOS Pointer Range for the Pentium
®
4 and the
Intel
®
Xeon
®
Processor Family
The registers in the LBR MSR stack and the MSR_LASTBRANCH_TOS MSR are read-
only and can be read using the RDMSR instruction.
Figure 16-13 shows the layout of a branch record in an LBR MSR (or MSR pair). Each
branch record consists of two linear addresses, which represent the “from” and “to”
instruction pointers for a branch, interrupt, or exception. The contents of the from
and to addresses differ, depending on the source of the branch:
• Taken branch — If the record is for a taken branch, the “from” address is the
address of the branch instruction and the “to” address is the target instruction of
the branch.
• Interrupt — If the record is for an interrupt, the “from” address the return
instruction pointer (RIP) saved for the interrupt and the “to” address is the
address of the first instruction in the interrupt handler routine. The RIP is the
linear address of the next instruction to be executed upon returning from the
interrupt handler.
• Exception — If the record is for an exception, the “from” address is the linear
address of the instruction that caused the exception to be generated and the “to”
address is the address of the first instruction in the exception handler routine.
DisplayFamily_DisplayModel Size of LBR Stack Range of TOS Pointer
Family 0FH, Models 0H-02H;
MSRs at locations 1DBH-
1DEH.
40 to 3
Family 0FH, Models; MSRs at
locations 680H-68FH.
16 0 to 15
Family 0FH, Model 03H; MSRs
at locations 6C0H-6CFH.
16 0 to 15