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Vol. 3 19-13
ARCHITECTURE COMPATIBILITY
ters. The only affect may be in how software handles the tags in the tag word (see
also: Section 19.18.4, “x87 FPU Tag Word”).
19.18.6 Floating-Point Exceptions
This section identifies the implementation differences in exception handling for
floating-point instructions in the various x87 FPUs and math coprocessors.
19.18.6.1 Denormal Operand Exception (#D)
When the denormal operand exception is masked, the 32-bit x87 FPUs automatically
normalize denormalized numbers when possible; whereas, the 16-bit IA-32 math
coprocessors return a denormal result. A program written to run on a 16-bit IA-32
math coprocessor that uses the denormal exception solely to normalize denormal
-
ized operands is redundant when run on the 32-bit x87 FPUs. If such a program is run
on 32-bit x87 FPUs, performance can be improved by masking the denormal excep
-
tion. Floating-point programs run faster when the FPU performs normalization of
denormalized operands.
The denormal operand exception is not raised for transcendental instructions and the
FXTRACT instruction on the 16-bit IA-32 math coprocessors. This exception is raised
for these instructions on the 32-bit x87 FPUs. The exception handlers ported to these
latter processors need to be changed only if the handlers gives special treatment to
different opcodes.
19.18.6.2 Numeric Overflow Exception (#O)
On the 32-bit x87 FPUs, when the numeric overflow exception is masked and the
rounding mode is set to chop (toward 0), the result is the largest positive or smallest
negative number. The 16-bit IA-32 math coprocessors do not signal the overflow
exception when the masked response is not ∞; that is, they signal overflow only
when the rounding control is not set to round to 0. If rounding is set to chop (toward
0), the result is positive or negative ∞. Under the most common rounding modes, this
difference has no impact on existing software.
If rounding is toward 0 (chop), a program on a 32-bit x87 FPU produces, under over-
flow conditions, a result that is different in the least significant bit of the significand,
compared to the result on a 16-bit IA-32 math coprocessor. The reason for this differ-
ence is IEEE Standard 754 compatibility.
When the overflow exception is not masked, the precision exception is flagged on the
32-bit x87 FPUs. When the result is stored in the stack, the significand is rounded
according to the precision control (PC) field of the FPU control word or according to
the opcode. On the 16-bit IA-32 math coprocessors, the precision exception is not
flagged and the significand is not rounded. The impact on existing software is that if
the result is stored on the stack, a program running on a 32-bit x87 FPU produces a
different result under overflow conditions than on a 16-bit IA-32 math coprocessor.