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Vol. 3 16-21
DEBUGGING, PROFILING BRANCHES AND TIME-STAMP COUNTER
16.4.8.3 Last Exception Records and Intel 64 Architecture
Intel 64 and IA-32 processors also provide MSRs that store the branch record for the
last branch taken prior to an exception or an interrupt. The location of the last excep-
tion record (LER) MSRs are model specific. The MSRs that store last exception
records are 64-bits. If IA-32e mode is disabled, only the lower 32-bits of the address
is recorded. If IA-32e mode is enabled, the processor writes 64-bit values into the
MSR. In 64-bit mode, last exception records store 64-bit addresses; in compatibility
mode, the upper 32-bits of last exception records are cleared.
16.4.9 BTS and DS Save Area
The Debug store (DS) feature flag (bit 21), returned by CPUID.1:EDX[21] Indicates
that the processor provides the debug store (DS) mechanism. This mechanism
allows BTMs to be stored in a memory-resident BTS buffer. See Section 16.4.5,
“Branch Trace Store (BTS).” Precise event-based sampling (PEBS, see Section
30.4.4, “Precise Event Based Sampling (PEBS),”) also uses the DS save area
provided by debug store mechanism. When CPUID.1:EDX[21] is set, the following
BTS facilities are available:
• The BTS_UNAVAILABLE flag in the IA32_MISC_ENABLE MSR indicates (when
clear) the availability of the BTS facilities, including the ability to set the BTS and
BTINT bits in the MSR_DEBUGCTLA MSR.
• The IA32_DS_AREA MSR can be programmed to point to the DS save area.
The debug store (DS) save area is a software-designated area of memory that is
used to collect the following two types of information:
• Branch records — When the BTS flag in the IA32_DEBUGCTL MSR is set, a
branch record is stored in the BTS buffer in the DS save area whenever a taken
branch, interrupt, or exception is detected.
• PEBS records — When a performance counter is configured for PEBS, a PEBS
record is stored in the PEBS buffer in the DS save area after the counter overflow
occurs. This record contains the architectural state of the processor (state of the
8 general purpose registers, EIP register, and EFLAGS register) at the next
occurrence of the PEBS event that caused the counter to overflow. When the
state information has been logged, the counter is automatically reset to a
preselected value, and event counting begins again. This feature is available only
for a subset of the performance events on processors that support PEBS.
NOTES
DS save area and recording mechanism is not available in the SMM.
The feature is disabled on transition to the SMM mode. Similarly DS
recording is disabled on the generation of a machine check exception