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Vol. 3 4-27
PAGING
Table 4-13. Format of an IA-32e PML4 Entry (PML4E) that References a Page-
Directory-Pointer Table
Bit
Position(s)
Contents
0 (P) Present; must be 1 to reference a page-directory-pointer table
1 (R/W) Read/write; if 0, writes may not be allowed to the 512-GByte region controlled by
this entry (depends on CPL and CR0.WP; see Section 4.6)
2 (U/S) User/supervisor; if 0, accesses with CPL=3 are not allowed to the 512-GByte
region controlled by this entry (see Section 4.6)
3 (PWT) Page-level write-through; indirectly determines the memory type used to access
the page-directory-pointer table referenced by this entry (see Section 4.9)
4 (PCD) Page-level cache disable; indirectly determines the memory type used to access
the page-directory-pointer table referenced by this entry (see Section 4.9)
5 (A) Accessed; indicates whether this entry has been used for linear-address
translation (see Section 4.8)
6Ignored
7 (PS) Reserved (must be 0)
11:8 Ignored
M–1:12 Physical address of 4-KByte aligned page-directory-pointer table referenced by
this entry
51:M Reserved (must be 0)
62:52 Ignored
63 (XD) If IA32_EFER.NXE = 1, execute-disable (if 1, instruction fetches are not allowed
from the 512-GByte region controlled by this entry; see Section 4.6); otherwise,
reserved (must be 0)