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8-36 Vol. 3
MULTIPLE-PROCESSOR MANAGEMENT
number of addressable IDs attributable to processor cores (Y) in the physical
package.
• Extended Processor Topology Enumeration parameters for 32-bit APIC
ID: Intel 64 processors supporting CPUID leaf 0BH will assign unique APIC IDs to
each logical processor in the system. CPUID leaf 0BH reports the 32-bit APIC ID
and provide topology enumeration parameters. See CPUID instruction reference
pages in
Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 2A.
The CPUID feature flag may indicate support for hardware multi-threading when only
one logical processor available in the package. In this case, the decimal value repre
-
sented by bits 16 through 23 in the EBX register will have a value of 1.
Software should note that the number of logical processors enabled by system soft-
ware may be less than the value of “Addressable IDs for Logical processors”. Simi-
larly, the number of cores enabled by system software may be less than the value of
“Addressable IDs for processor cores”.
Software can detect the availability of the CPUID extended topology enumeration leaf
(0BH) by performing two steps:
• Check maximum input value for basic CPUID information by executing CPUID
with EAX= 0. If CPUID.0H:EAX is greater than or equal or 11 (0BH), then proceed
to next step,
• Check CPUID.EAX=0BH, ECX=0H:EBX is non-zero.
If both of the above conditions are true, extended topology enumeration leaf is avail-
able. Note the presence of CPUID leaf 0BH in a processor does not guarantee support
that the local APIC supports x2APIC. If CPUID.(EAX=0BH, ECX=0H):EBX returns
zero and maximum input value for basic CPUID information is greater than 0BH, then
CPUID.0BH leaf is not supported on that processor.
8.6.1 Initializing Processors
Supporting Hyper-Threading Technology
The initialization process for an MP system that contains processors supporting Intel
Hyper-Threading Technology is the same as for conventional MP systems (see
Section 8.4, “Multiple-Processor (MP) Initialization”). One logical processor in the
system is selected as the BSP and other processors (or logical processors) are desig-
nated as APs. The initialization process is identical to that described in Section 8.4.3,
“MP Initialization Protocol Algorithm for Intel Xeon Processors,” and Section 8.4.4,
“MP Initialization Example.”
3. Software must check CPUID for its support of leaf 4 when implementing support for multi-core. If
CPUID leaf 4 is not available at runtime, software should handle the situation as if there is only
one core per package.
4. Maximum number of cores in the physical package must be queried by executing CPUID with
EAX=4 and a valid ECX input value. Valid ECX input values start from 0.