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16-34 Vol. 3
DEBUGGING, PROFILING BRANCHES AND TIME-STAMP COUNTER
• Branch trace store and CPL-qualified BTS — See Section 16.4.6 and Section
16.4.5.
• FREEZE_LBRS_ON_PMI flag (bit 11) — see Section 16.4.7.
• FREEZE_PERFMON_ON_PMI flag (bit 12) — see Section 16.4.7.
• FREEZE_WHILE_SMM_EN (bit 14) — FREEZE_WHILE_SMM_EN is supported
if IA32_PERF_CAPABILITIES.FREEZE_WHILE_SMM[Bit 12] is reporting 1. See
Section 16.4.1.
Processors based on Intel microarchitecture (Nehalem) provide additional capabili-
ties:
• Independent control of uncore PMI — The IA32_DEBUGCTL MSR provides a
bit field (see Figure 16-11) for software to enable each logical processor to
receive an uncore counter overflow interrupt.
• LBR filtering — Processors based on Intel microarchitecture (Nehalem) support
filtering of LBR based on combination of CPL and branch type conditions. When
LBR filtering is enabled, the LBR stack only captures the subset of branches that
are specified by MSR_LBR_SELECT.
16.6.1 LBR Stack
Processors based on Intel microarchitecture (Nehalem) provide 16 pairs of MSR to
record last branch record information. The layout of each MSR pair is shown in
Table 16-6 and Table 16-7.
Figure 16-11. IA32_DEBUGCTL MSR for Processors based
on Intel microarchitecture (Nehalem)
31
TR — Trace messages enable
BTINT — Branch trace interrupt
BTF — Single-step on branches
LBR — Last branch/interrupt/exception
Reserved
87654321 0
BTS — Branch trace store
Reserved
910
BTS_OFF_OS — BTS off in OS
BTS_OFF_USR — BTS off in user code
FREEZE_LBRS_ON_PMI
FREEZE_PERFMON_ON_PMI
11
12
14
FREEZE_WHILE_SMM_EN
UNCORE_PMI_EN
13