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Vol. 3 8-9
MULTIPLE-PROCESSOR MANAGEMENT
among processors are explicitly required to obey program ordering through the use
of appropriate locking or serializing operations (see Section 8.2.5, “Strengthening or
Weakening the Memory-Ordering Model”).
8.2.2 Memory Ordering in P6 and More Recent Processor Families
The Intel Core 2 Duo, Intel Atom, Intel Core Duo, Pentium 4, and P6 family proces-
sors also use a processor-ordered memory-ordering model that can be further
defined as “write ordered with store-buffer forwarding.” This model can be character-
ized as follows.
In a single-processor system for memory regions defined as write-back cacheable,
the memory-ordering model respects the following principles (Note the memory-
ordering principles for single-processor and multiple-processor systems are written
from the perspective of software executing on the processor, where the term
“processor“ refers to a logical processor. For example, a physical processor
supporting multiple cores and/or HyperThreading Technology is treated as a multi-
processor systems.):
• Reads are not reordered with other reads.
• Writes are not reordered with older reads.
• Writes to memory are not reordered with other writes, with the exception of
— writes executed with the CLFLUSH instruction,
— streaming stores (writes) executed with the non-temporal move instructions
(MOVNTI, MOVNTQ, MOVNTDQ, MOVNTPS, and MOVNTPD),
— string operations (see Section 8.2.4.1).
• Reads may be reordered with older writes to different locations but not with older
writes to the same location.
• Reads or writes cannot be reordered with I/O instructions, locked instructions, or
serializing instructions.
• Reads cannot pass LFENCE and MFENCE instructions.
• Writes cannot pass SFENCE and MFENCE instructions.
In a multiple-processor system, the following ordering principles apply:
• Individual processors use the same ordering principles as in a single-processor
system.
• Writes by a single processor are observed in the same order by all processors.
• Writes from an individual processor are NOT ordered with respect to the writes
from other processors.
• Memory ordering obeys causality (memory ordering respects transitive
visibility).
• Any two stores are seen in a consistent order by processors other than those
performing the stores