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Vol. 3 4-29
PAGING
— Bits 51:21 are from the PDE.
— Bits 20:0 are from the original linear address.
• If the PDE’s PS flag is 0, a 4-KByte naturally aligned page table is located at the
physical address specified in bits 51:12 of the PDE (see Table 4-16). A page table
2 (U/S) User/supervisor; if 0, accesses with CPL=3 are not allowed to the 2-MByte page
referenced by this entry (see Section 4.6)
3 (PWT) Page-level write-through; indirectly determines the memory type used to access
the 2-MByte page referenced by this entry (see Section 4.9)
4 (PCD) Page-level cache disable; indirectly determines the memory type used to access
the 2-MByte page referenced by this entry (see Section 4.9)
5 (A) Accessed; indicates whether software has accessed the 2-MByte page referenced
by this entry (see Section 4.8)
6 (D) Dirty; indicates whether software has written to the 2-MByte page referenced by
this entry (see Section 4.8)
7 (PS) Page size; must be 1 (otherwise, this entry references a page table; see
Table 4-16)
8 (G) Global; if CR4.PGE = 1, determines whether the translation is global (see Section
4.10); ignored otherwise
11:9 Ignored
12 (PAT) Indirectly determines the memory type used to access the 2-MByte page
referenced by this entry (see Section 4.9)
1
20:13 Reserved (must be 0)
M–1:21 Physical address of the 2-MByte page referenced by this entry
51:M Reserved (must be 0)
62:52 Ignored
63 (XD) If IA32_EFER.NXE = 1, execute-disable (if 1, instruction fetches are not allowed
from the 2-MByte page controlled by this entry; see Section 4.6); otherwise,
reserved (must be 0)
NOTES:
1. The PAT is supported on all processors that support IA-32e paging.
Table 4-15. Format of an IA-32e Page-Directory Entry that Maps a 2-MByte Page
Bit
Position(s)
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