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Vol. 3 8-71
MULTIPLE-PROCESSOR MANAGEMENT
}
8.10.6.3 Halt Idle Logical Processors
If one of two logical processors is idle or in a spin-wait loop of long duration, explicitly
halt that processor by means of a HLT instruction.
In an MP system, operating systems can place idle processors into a loop that contin-
uously checks the run queue for runnable software tasks. Logical processors that
execute idle loops consume a significant amount of core’s execution resources that
might otherwise be used by the other logical processors in the physical package. For
this reason, halting idle logical processors optimizes the performance.
8
If all logical
processors within a physical package are halted, the processor will enter a power-
saving state.
8.10.6.4 Potential Usage of MONITOR/MWAIT in C1 Idle Loops
An operating system may also consider replacing HLT with MONITOR/MWAIT in its C1
idle loop. An example is shown in Example 8-26:
Example 8-26. An OS Idle Loop with MONITOR/MWAIT in the C1 Idle Loop
// WorkQueue is a memory location indicating there is a thread
// ready to run. A non-zero value for WorkQueue is assumed to
// indicate the presence of work to be scheduled on the processor.
// The following example assumes that the necessary padding has been
// added surrounding WorkQueue to eliminate false wakeups
// The idle loop is entered with interrupts disabled.
WHILE (1) {
IF (WorkQueue) THEN {
// Schedule work at WorkQueue
} ELSE {
// No work to do - wait in appropriate C-state handler depending
// on Idle time accumulated
IF (IdleTime >= IdleTimeThreshhold) THEN {
// Call appropriate C1, C2, C3 state handler, C1
// handler shown below
}
}
}
// C1 handler uses a Halt instruction
VOID C1Handler()
8. Excessive transitions into and out of the HALT state could also incur performance penalties.
Operating systems should evaluate the performance trade-offs for their operating system.