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Vol. 3 15-5
MACHINE-CHECK ARCHITECTURE
Section 15.6), and IA32_MCi_STATUS MSR bits 56:55 are used to report the
signaling of uncorrected recoverable errors and whether software must take
recovery actions for uncorrected errors. Note that when MCG_TES_P is not set,
bits 56:53 of the IA32_MCi_STATUS MSR are model-specific. If MCG_TES_P is set
but MCG_SER_P is not set, bits 56:55 are reserved.
The effect of writing to the IA32_MCG_CAP MSR is undefined.
15.3.1.2 IA32_MCG_STATUS MSR
The IA32_MCG_STATUS MSR describes the current state of the processor
after a machine-check exception has occurred (see
Figure 15-3).
Where:
• RIPV (restart IP valid) flag, bit 0 — Indicates (when set) that program
execution can be restarted reliably at the instruction pointed to by the instruction
pointer pushed on the stack when the machine-check exception is generated.
When clear, the program cannot be reliably restarted at the pushed instruction
pointer.
• EIPV (error IP valid) flag, bit 1 — Indicates (when set) that the instruction
pointed to by the instruction pointer pushed onto the stack when the machine-
check exception is generated is directly associated with the error. When this flag
is cleared, the instruction pointed to may not be associated with the error.
• MCIP (machine check in progress) flag, bit 2 — Indicates (when set) that a
machine-check exception was generated. Software can set or clear this flag. The
occurrence of a second Machine-Check Event while MCIP is set will cause the
processor to enter a shutdown state. For information on processor behavior in
the shutdown state, please refer to the description in
Chapter 6, “Interrupt and
Exception Handling”: “Interrupt 8—Double Fault Exception (#DF)”.
Bits 63:03 in IA32_MCG_STATUS are reserved.
Figure 15-3. IA32_MCG_STATUS Register
EIPV—Error IP valid flag
MCIP—Machine check in progress flag
63 0
Reserved
123
E
I
P
V
M
C
I
P
R
I
P
V
RIPV—Restart IP valid flag