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Vol. 3 4-31
PAGING
— Bits 11:0 are from the original linear address.
If a paging-structure entry’s P flag (bit 0) is 0 or if the entry sets any reserved bit, the
entry is used neither to reference another paging-structure entry nor to map a page.
A reference using a linear address whose translation would use such a paging-struc-
ture entry causes a page-fault exception (see Section 4.7).
The following bits are reserved with IA-32e paging:
• If the P flag of a paging-structure entry is 1, bits 51:MAXPHYADDR are reserved.
Table 4-17. Format of an IA-32e Page-Table Entry that Maps a 4-KByte Page
Bit
Position(s)
Contents
0 (P) Present; must be 1 to map a 4-KByte page
1 (R/W) Read/write; if 0, writes may not be allowed to the 4-KByte page referenced by this
entry (depends on CPL and CR0.WP; see Section 4.6)
2 (U/S) User/supervisor; if 0, accesses with CPL=3 are not allowed to the 4-KByte page
referenced by this entry (see Section 4.6)
3 (PWT) Page-level write-through; indirectly determines the memory type used to access
the 4-KByte page referenced by this entry (see Section 4.9)
4 (PCD) Page-level cache disable; indirectly determines the memory type used to access
the 4-KByte page referenced by this entry (see Section 4.9)
5 (A) Accessed; indicates whether software has accessed the 4-KByte page referenced
by this entry (see Section 4.8)
6 (D) Dirty; indicates whether software has written to the 4-KByte page referenced by
this entry (see Section 4.8)
7 (PAT) Indirectly determines the memory type used to access the 2-MByte page
referenced by this entry (see Section 4.9)
8 (G) Global; if CR4.PGE = 1, determines whether the translation is global (see Section
4.10); ignored otherwise
11:9 Ignored
M–1:12 Physical address of the 4-KByte page referenced by this entry
51:M Reserved (must be 0)
62:52 Ignored
63 (XD) If IA32_EFER.NXE = 1, execute-disable (if 1, instruction fetches are not allowed
from the 4-KByte page controlled by this entry; see Section 4.6); otherwise,
reserved (must be 0)