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16-24 Vol. 3
DEBUGGING, PROFILING BRANCHES AND TIME-STAMP COUNTER
• PEBS counter reset value — A 40-bit value that the counter is to be reset to
after state information has collected following counter overflow. This value allows
state information to be collected after a preset number of events have been
counted.
Figures 16-6 shows the structure of a 12-byte branch record in the BTS buffer. The
fields in each record are as follows:
• Last branch from — Linear address of the instruction from which the branch,
interrupt, or exception was taken.
• Last branch to — Linear address of the branch target or the first instruction in
the interrupt or exception service routine.
• Branch predicted — Bit 4 of field indicates whether the branch that was taken
was predicted (set) or not predicted (clear).
Figures 16-7 shows the structure of the 40-byte PEBS records. Nominally the register
values are those at the beginning of the instruction that caused the event. However,
there are cases where the registers may be logged in a partially modified state. The
linear IP field shows the value in the EIP register translated from an offset into the
current code segment to a linear address.
Figure 16-6. 32-bit Branch Trace Record Format
Last Branch From
Last Branch To
Branch Predicted
0H
4H
8H
0
31
4