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CONTENTS
xlii Vol. 3A
PAGE
Table 30-1. UMask and Event Select Encodings for Pre-Defined
Architectural Performance Events30-13
Table 30-2. Core Specificity Encoding within a Non-Architectural Umask. . . . . . . . . . . . . . . . . .30-15
Table 30-3. Agent Specificity Encoding within a Non-Architectural Umask . . . . . . . . . . . . . . . .30-15
Table 30-4. HW Prefetch Qualification Encoding within a Non-Architectural Umask. . . . . . . .30-16
Table 30-5. MESI Qualification Definitions within a Non-Architectural Umask. . . . . . . . . . . . . .30-16
Table 30-6. Bus Snoop Qualification Definitions within a Non-Architectural Umask . . . . . . . .30-17
Table 30-7. Snoop Type Qualification Definitions within a Non-Architectural Umask. . . . . . .30-17
Table 30-8. Association of Fixed-Function Performance Counters with
Architectural Performance Events30-18
Table 30-10. PEBS Performance Events for Intel Core Microarchitecture. . . . . . . . . . . . . . . . . . .30-22
Table 30-9. At-Retirement Performance Events for Intel Core Microarchitecture. . . . . . . . . .30-22
Table 30-11. Requirements to Program PEBS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30-24
Table 30-12. PEBS Record Format for Intel Core i7 Processor Family . . . . . . . . . . . . . . . . . . . . . .30-28
Table 30-13. Data Source Encoding for Load Latency Record. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30-33
Table 30-14. Off-Core Response Event Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30-35
Table 30-15. MSR_OFFCORE_RSP_Z Bit Field Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30-35
Table 30-16. Opcode Field Encoding for MSR_UNCORE_ADDR_OPCODE_MATCH. . . . . . . . . . . .30-42
Table 30-17. Performance Counter MSRs and Associated CCCR and
ESCR MSRs (Pentium 4 and Intel Xeon Processors)30-45
Table 30-18. Event Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30-54
Table 30-19. CCR Names and Bit Positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30-60
Table 30-20. Effect of Logical Processor and CPL Qualification
for Logical-Processor-Specific (TS) Events30-73
Table 30-21. Effect of Logical Processor and CPL Qualification
for Non-logical-Processor-specific (TI) Events30-74
Table A-1. Architectural Performance Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2
Table A-2. Non-Architectural Performance Events In the Processor Core for Intel Core i7
Processor and Intel Xeon Processor 5500 SeriesA-2
Table A-3. Non-Architectural Performance Events In the Processor Uncore for Intel Core i7
Processor and Intel Xeon Processor 5500 SeriesA-35
Table A-4. Non-Architectural Performance Events In Next Generation Processor Core
(Codenamed Westmere)A-58
Table A-5. Non-Architectural Performance Events for Processors based on Enhanced Intel Core
MicroarchitectureA-88
Table A-6. Fixed-Function Performance Counter
and Pre-defined Performance EventsA-89
Table A-7. Non-Architectural Performance Events
in Processors Based on Intel Core MicroarchitectureA-90
Table A-8. Non-Architectural Performance Events for Intel Atom Processors . . . . . . . . . . . .A-133
Table A-9. Non-Architectural Performance Events
in Intel Core Solo and Intel Core Duo ProcessorsA-156
Table A-10. Performance Monitoring Events Supported by Intel NetBurst Microarchitecture for
Non-Retirement CountingA-165
Table A-11. Performance Monitoring Events For Intel NetBurst
Microarchitecture for At-Retirement CountingA-197
Table A-12. Intel NetBurst Microarchitecture Model-Specific Performance Monitoring Events (For
Model Encoding 3, 4 or 6)A-204
Table A-14. List of Metrics Available for Execution Tagging
(For Execution Event Only)A-205
Table A-13. List of Metrics Available for Front_end Tagging
(For Front_end Event Only)A-205