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9-46 Vol. 3
PROCESSOR MANAGEMENT AND INITIALIZATION
• ECX contains 79H (address of IA32_BIOS_UPDT_TRIG).
Other requirements are:
• If the update is loaded while the processor is in real mode, then the update data
may not cross a segment boundary.
• If the update is loaded while the processor is in real mode, then the update data
may not exceed a segment limit.
• If paging is enabled, pages that are currently present must map the update data.
• The microcode update data requires a 16-byte boundary alignment.
9.11.6.1 Hard Resets in Update Loading
The effects of a loaded update are cleared from the processor upon a hard reset.
Therefore, each time a hard reset is asserted during the BIOS POST, the update must
be reloaded on all processors that observed the reset. The effects of a loaded update
are, however, maintained across a processor INIT. There are no side effects caused
by loading an update into a processor multiple times.
9.11.6.2 Update in a Multiprocessor System
A multiprocessor (MP) system requires loading each processor with update data
appropriate for its CPUID and platform ID bits. The BIOS is responsible for ensuring
that this requirement is met and that the loader is located in a module executed by
all processors in the system. If a system design permits multiple steppings of
Pentium 4, Intel Xeon, and P6 family processors to exist concurrently; then the BIOS
must verify individual processors against the update header information to ensure
appropriate loading. Given these considerations, it is most practical to load the
update during MP initialization.
9.11.6.3 Update in a System Supporting Intel Hyper-Threading Technology
Intel Hyper-Threading Technology has implications on the loading of the microcode
update. The update must be loaded for each core in a physical processor. Thus, for a
processor supporting Intel Hyper-Threading Technology, only one logical processor
per core is required to load the microcode update. Each individual logical processor
can independently load the update. However, MP initialization must provide some
mechanism (e.g. a software semaphore) to force serialization of microcode update
loads and to prevent simultaneous load attempts to the same core.
9.11.6.4 Update in a System Supporting Dual-Core Technology
Dual-core technology has implications on the loading of the microcode update. The
microcode update facility is not shared between processor cores in the same physical
package. The update must be loaded for each core in a physical processor.