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Vol. 3 16-45
DEBUGGING, PROFILING BRANCHES AND TIME-STAMP COUNTER
For more detail on these capabilities, see Section 16.7.3, “Last Exception Records,”
and Appendix B.7, “MSRs In the Pentium M Processor.”
16.10 LAST BRANCH, INTERRUPT, AND EXCEPTION
RECORDING (P6 FAMILY PROCESSORS)
The P6 family processors provide five MSRs for recording the last branch, interrupt,
or exception taken by the processor: DEBUGCTLMSR, LastBranchToIP, LastBranch-
FromIP, LastExceptionToIP, and LastExceptionFromIP. These registers can be used to
collect last branch records, to set breakpoints on branches, interrupts, and excep-
tions, and to single-step from one branch to the next.
See Appendix B, “Model-Specific Registers (MSRs),” for a detailed description of each
of the last branch recording MSRs.
16.10.1 DEBUGCTLMSR Register
The version of the DEBUGCTLMSR register found in the P6 family processors enables
last branch, interrupt, and exception recording; taken branch breakpoints; the
breakpoint reporting pins; and trace messages. This register can be written to using
the WRMSR instruction, when operating at privilege level 0 or when in real-address
mode. A protected-mode operating system procedure is required to provide user
access to this register. Figure 16-18 shows the flags in the DEBUGCTLMSR register
for the P6 family processors. The functions of these flags are as follows:
• LBR (last branch/interrupt/exception) flag (bit 0) — When set, the
processor records the source and target addresses (in the LastBranchToIP,
LastBranchFromIP, LastExceptionToIP, and LastExceptionFromIP MSRs) for the
last branch and the last exception or interrupt taken by the processor prior to a
debug exception being generated. The processor clears this flag whenever a
debug exception, such as an instruction or data breakpoint or single-step trap
occurs.
Figure 16-17. LBR Branch Record Layout for the Pentium M Processor
0
63
From Linear Address
To Linear Address
32 - 31
MSR_LASTBRANCH_0 through MSR_LASTBRANCH_7