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6-56 Vol. 3
INTERRUPT AND EXCEPTION HANDLING
second page fault can occur.
1
If a page fault is caused by a page-level protection
violation, the access flag in the page-directory entry is set when the fault occurs.
The behavior of IA-32 processors regarding the access flag in the corresponding
page-table entry is model specific and not architecturally defined.
Saved Instruction Pointer
The saved contents of CS and EIP registers generally point to the instruction that
generated the exception. If the page-fault exception occurred during a task switch,
the CS and EIP registers may point to the first instruction of the new task (as
described in the following “Program State Change” section).
Program State Change
A program-state change does not normally accompany a page-fault exception,
because the instruction that causes the exception to be generated is not executed.
After the page-fault exception handler has corrected the violation (for example,
loaded the missing page into memory), execution of the program or task can be
resumed.
When a page-fault exception is generated during a task switch, the program-state
may change, as follows. During a task switch, a page-fault exception can occur
during any of following operations:
• While writing the state of the original task into the TSS of that task.
• While reading the GDT to locate the TSS descriptor of the new task.
• While reading the TSS of the new task.
• While reading segment descriptors associated with segment selectors from the
new task.
• While reading the LDT of the new task to verify the segment registers stored in
the new TSS.
In the last two cases the exception occurs in the context of the new task. The instruc-
tion pointer refers to the first instruction of the new task, not to the instruction which
caused the task switch (or the last instruction to be executed, in the case of an inter
-
rupt). If the design of the operating system permits page faults to occur during task-
switches, the page-fault handler should be called through a task gate.
If a page fault occurs during a task switch, the processor will load all the state infor-
mation from the new TSS (without performing any additional limit, present, or type
checks) before it generates the exception. The page-fault handler should thus not
rely on being able to use the segment selectors found in the CS, SS, DS, ES, FS, and
GS registers without causing another exception. (See the Program State Change
1. Processors update CR2 whenever a page fault is detected. If a second page fault occurs while an
earlier page fault is being delivered, the faulting linear address of the second fault will overwrite
the contents of CR2 (replacing the previous address). These updates to CR2 occur even if the
page fault results in a double fault or occurs during the delivery of a double fault.