Filter
Top Products
4-34 Vol. 3
PAGING
both the R/W flag and the U/S flag are 1 in every paging-structure entry
controlling the translation.
— Instruction fetches.
• For 32-bit paging or if IA32_EFER.NXE = 0, instructions may be fetched
from any linear address with a valid translation for which the U/S flag is 1
in every paging-structure entry controlling the translation.
• For PAE paging or IA-32e paging with IA32_EFER.NXE = 1, instructions
may be fetched from any linear address with a valid translation for which
the U/S flag is 1 and the XD flag is 0 in every paging-structure entry
controlling the translation.
A processor may cache information from the paging-structure entries in TLBs and
paging-structure caches (see Section 4.10). These structures may include informa-
tion about access rights. The processor may enforce access rights based on the TLBs
and paging-structure caches instead of on the paging structures in memory.
This fact implies that, if software modifies a paging-structure entry to change access
rights, the processor might not use that change for a subsequent access to an
affected linear address (see Section 4.10.3.3). See Section 4.10.3.2 for how soft-
ware can ensure that the processor uses the modified access rights.
4.7 PAGE-FAULT EXCEPTIONS
Accesses using linear addresses may cause page-fault exceptions (#PF; exception
14). An access to a linear address may cause page-fault exception for either of two
reasons: (1) there is no valid translation for the linear address; or (2) there is a valid
translation for the linear address, but its access rights do not permit the access.
As noted in Section 4.3, Section 4.4.2, and Section 4.5, there is no valid translation
for a linear address if the translation process for that address would use a paging-
structure entry in which the P flag (bit 0) is 0 or one that sets a reserved bit. If there
is a valid translation for a linear address, its access rights are determined as specified
in Section 4.6.
Figure 4-11 illustrates the error code that the processor provides on delivery of a
page-fault exception. The following items explain how the bits in the error code
describe the nature of the page-fault exception:
• P flag (bit 0).
This flag is 0 if there is no valid translation for the linear address because the P
flag was 0 in one of the paging-structure entries used to translate that address.
• W/R (bit 1).
If the access causing the page-fault exception was a write, this flag is 1;
otherwise, it is 0. This flag describes the access causing the page-fault exception,
not the access rights specified by paging.
• U/S (bit 2).
If a supervisor-mode (CPL < 3) access caused the page-fault exception, this flag