Intel 253668-032US Webcam User Manual


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Vol. 3A xxxvii
CONTENTS
PAGE
Figure 29-1. Host External Interrupts and Guest Virtual Interrupts . . . . . . . . . . . . . . . . . . . . . . . . .29-5
Figure 30-1. Layout of IA32_PERFEVTSELx MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30-4
Figure 30-2. Layout of IA32_FIXED_CTR_CTRL MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30-7
Figure 30-3. Layout of IA32_PERF_GLOBAL_CTRL MSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30-8
Figure 30-4. Layout of IA32_PERF_GLOBAL_STATUS MSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30-9
Figure 30-5. Layout of IA32_PERF_GLOBAL_OVF_CTRL MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30-9
Figure 30-6. Layout of IA32_PERFEVTSELx MSRs Supporting Architectural Performance
Monitoring Version 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-10
Figure 30-7. Layout of IA32_FIXED_CTR_CTRL MSR Supporting Architectural Performance
Monitoring Version 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-11
Figure 30-8. Layout of Global Performance Monitoring Control MSR . . . . . . . . . . . . . . . . . . . . . . 30-12
Figure 30-9. Layout of MSR_PERF_FIXED_CTR_CTRL MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-19
Figure 30-10. Layout of MSR_PERF_GLOBAL_CTRL MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-20
Figure 30-11. Layout of MSR_PERF_GLOBAL_STATUS MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-20
Figure 30-12. Layout of MSR_PERF_GLOBAL_OVF_CTRL MSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-21
Figure 30-13. Layout of IA32_PEBS_ENABLE MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-28
Figure 30-14. PEBS Programming Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-30
Figure 30-15. Layout of MSR_PEBS_LD_LAT MSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-34
Figure 30-16. Layout of MSR_OFFCORE_RSP_0 and MSR_OFFCORE_RSP_1 to Configure Off-core
Response Events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-35
Figure 30-17. Layout of MSR_UNCORE_PERF_GLOBAL_CTRL MSR. . . . . . . . . . . . . . . . . . . . . . . . . 30-38
Figure 30-18. Layout of MSR_UNCORE_PERF_GLOBAL_STATUS MSR. . . . . . . . . . . . . . . . . . . . . . 30-39
Figure 30-19. Layout of MSR_UNCORE_PERF_GLOBAL_OVF_CTRL MSR . . . . . . . . . . . . . . . . . . . 30-39
Figure 30-20. Layout of MSR_UNCORE_PERFEVTSELx MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-40
Figure 30-21. Layout of MSR_UNCORE_FIXED_CTR_CTRL MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-41
Figure 30-22. Layout of MSR_UNCORE_ADDR_OPCODE_MATCH MSR . . . . . . . . . . . . . . . . . . . . . . 30-42
Figure 30-23. Event Selection Control Register (ESCR) for Pentium 4
and Intel Xeon Processors without Intel HT Technology Support. . . . . . . . . . . . . 30-49
Figure 30-24. Performance Counter (Pentium 4 and Intel Xeon Processors) . . . . . . . . . . . . . . . . 30-51
Figure 30-25. Counter Configuration Control Register (CCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-52
Figure 30-26. Effects of Edge Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-58
Figure 30-27. Event Selection Control Register (ESCR) for the Pentium 4 Processor, Intel Xeon
Processor and Intel Xeon Processor MP Supporting Hyper-Threading Technology30-
69
Figure 30-28. Counter Configuration Control Register (CCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-71
Figure 30-29. Layout of IA32_PERF_CAPABILITIES MSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-79
Figure 30-30. Block Diagram of 64-bit Intel Xeon Processor MP with 8-MByte L3. . . . . . . . . . . 30-80
Figure 30-31. MSR_IFSB_IBUSQx, Addresses: 107CCH and 107CDH. . . . . . . . . . . . . . . . . . . . . . . . 30-81
Figure 30-32. MSR_IFSB_ISNPQx, Addresses: 107CEH and 107CFH. . . . . . . . . . . . . . . . . . . . . . . . 30-82
Figure 30-33. MSR_EFSB_DRDYx, Addresses: 107D0H and 107D1H . . . . . . . . . . . . . . . . . . . . . . . 30-83
Figure 30-34. MSR_IFSB_CTL6, Address: 107D2H;
MSR_IFSB_CNTR7, Address: 107D3H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-84
Figure 30-35. Block Diagram of Intel Xeon Processor 7400 Series . . . . . . . . . . . . . . . . . . . . . . . . . 30-85
Figure 30-36. Block Diagram of Intel Xeon Processor 7100 Series . . . . . . . . . . . . . . . . . . . . . . . . . 30-86
Figure 30-37. MSR_EMON_L3_CTR_CTL0/1, Addresses: 107CCH/107CDH . . . . . . . . . . . . . . . . . 30-88
Figure 30-38. MSR_EMON_L3_CTR_CTL2/3, Addresses: 107CEH/107CFH. . . . . . . . . . . . . . . . . . 30-91
Figure 30-39. MSR_EMON_L3_CTR_CTL4/5/6/7, Addresses: 107D0H-107D3H. . . . . . . . . . . . . 30-92
Figure 30-40. PerfEvtSel0 and PerfEvtSel1 MSRs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-95
Figure 30-41. CESR MSR (Pentium Processor Only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-99
Figure C-1. MP System With Multiple Pentium III Processors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-3
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