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17-30 Vol. 3
8086 EMULATION
cient means of handling maskable hardware interrupts that occur during a virtual-
8086 mode task. Also, because the IOPL value is less than 3 and the VIF flag is
enabled, the information pushed on the stack by the processor when invoking the
interrupt handler is slightly different between methods 5 and 6 (see
Table 17-2).
17.4 PROTECTED-MODE VIRTUAL INTERRUPTS
The IA-32 processors (beginning with the Pentium processor) also support the VIF
and VIP flags in the EFLAGS register in protected mode by setting the PVI (protected-
mode virtual interrupt) flag in the CR4 register. Setting the PVI flag allows applica
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tions running at privilege level 3 to execute the CLI and STI instructions without
causing a general-protection exception (#GP) or affecting hardware interrupts.
When the PVI flag is set to 1, the CPL is 3, and the IOPL is less than 3, the STI and
CLI instructions set and clear the VIF flag in the EFLAGS register, leaving IF unaf-
fected. In this mode of operation, an application running in protected mode and at a
CPL of 3 can inhibit interrupts in the same manner as is described in
Section 17.3.2,
“Class 2—Maskable Hardware Interrupt Handling in Virtual-8086 Mode Using the
Virtual Interrupt Mechanism”, for a virtual-8086 mode task. When the application
executes the CLI instruction, the processor clears the VIF flag. If the processor
receives a maskable hardware interrupt, the processor invokes the protected-mode
interrupt handler. This handler checks the state of the VIF flag in the EFLAGS register.
If the VIF flag is clear (indicating that the active task does not want to have interrupts
handled now), the handler sets the VIP flag in the EFLAGS image on the stack and
returns to the privilege-level 3 application, which continues program execution.
When the application executes a STI instruction to set the VIF flag, the processor
automatically invokes the general-protection exception handler, which can then
handle the pending interrupt. After handing the pending interrupt, the handler typi
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cally sets the VIF flag and clears the VIP flag in the EFLAGS image on the stack and
executes a return to the application program. The next time the processor receives a
maskable hardware interrupt, the processor will handle it in the normal manner for
interrupts received while the processor is operating at a CPL of 3.
As with the virtual mode extension (enabled with the VME flag in the CR4 register),
the protected-mode virtual interrupt extension only affects maskable hardware
interrupts (interrupt vectors 32 through 255). NMI interrupts and exceptions are
handled in the normal manner.
When protected-mode virtual interrupts are disabled (that is, when the PVI flag in
control register CR4 is set to 0, the CPL is less than 3, or the IOPL value is 3), then
the CLI and STI instructions execute in a manner compatible with the Intel486
processor. That is, if the CPL is greater (less privileged) than the I/O privilege level
(IOPL), a general-protection exception occurs. If the IOPL value is 3, CLI and STI
clear or set the IF flag, respectively.
PUSHF, POPF, IRET and INT are executed like in the Intel486 processor, regardless of
whether protected-mode virtual interrupts are enabled.