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17-2 Vol. 3
8086 EMULATION
The following is a summary of the core features of the real-address mode execution
environment as would be seen by a program written for the 8086:
• The processor supports a nominal 1-MByte physical address space (see Section
17.1.1, “Address Translation in Real-Address Mode”, for specific details). This
address space is divided into segments, each of which can be up to 64 KBytes in
length. The base of a segment is specified with a 16-bit segment selector, which
is zero extended to form a 20-bit offset from address 0 in the address space. An
operand within a segment is addressed with a 16-bit offset from the base of the
segment. A physical address is thus formed by adding the offset to the 20-bit
segment base (see
Section 17.1.1, “Address Translation in Real-Address Mode”).
• All operands in “native 8086 code” are 8-bit or 16-bit values. (Operand size
override prefixes can be used to access 32-bit operands.)
• Eight 16-bit general-purpose registers are provided: AX, BX, CX, DX, SP, BP, SI,
and DI. The extended 32 bit registers (EAX, EBX, ECX, EDX, ESP, EBP, ESI, and
EDI) are accessible to programs that explicitly perform a size override operation.
• Four segment registers are provided: CS, DS, SS, and ES. (The FS and GS
registers are accessible to programs that explicitly access them.) The CS register
contains the segment selector for the code segment; the DS and ES registers
contain segment selectors for data segments; and the SS register contains the
segment selector for the stack segment.
• The 8086 16-bit instruction pointer (IP) is mapped to the lower 16-bits of the EIP
register. Note this register is a 32-bit register and unintentional address wrapping
may occur.
• The 16-bit FLAGS register contains status and control flags. (This register is
mapped to the 16 least significant bits of the 32-bit EFLAGS register.)
• All of the Intel 8086 instructions are supported (see Section 17.1.3, “Instructions
Supported in Real-Address Mode”).
• A single, 16-bit-wide stack is provided for handling procedure calls and
invocations of interrupt and exception handlers. This stack is contained in the
stack segment identified with the SS register. The SP (stack pointer) register
contains an offset into the stack segment. The stack grows down (toward lower
segment offsets) from the stack pointer. The BP (base pointer) register also
contains an offset into the stack segment that can be used as a pointer to a
parameter list. When a CALL instruction is executed, the processor pushes the
current instruction pointer (the 16 least-significant bits of the EIP register and,
on far calls, the current value of the CS register) onto the stack. On a return,
initiated with a RET instruction, the processor pops the saved instruction pointer
from the stack into the EIP register (and CS register on far returns). When an
implicit call to an interrupt or exception handler is executed, the processor
pushes the EIP, CS, and EFLAGS (low-order 16-bits only) registers onto the
stack. On a return from an interrupt or exception handler, initiated with an IRET
instruction, the processor pops the saved instruction pointer and EFLAGS image
from the stack into the EIP, CS, and EFLAGS registers.