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Vol. 3 8-33
MULTIPLE-PROCESSOR MANAGEMENT
8.4.5 Identifying Logical Processors in an MP System
After the BIOS has completed the MP initialization protocol, each logical processor
can be uniquely identified by its local APIC ID. Software can access these APIC IDs in
either of the following ways:
• Read APIC ID for a local APIC — Code running on a logical processor can read
APIC ID in one of two ways depending on the local APIC unit is operating in
x2APIC mode (see
Intel® 64 Architecture x2APIC Specification)or in xAPIC
mode:
— If the local APIC unit supports x2APIC and is operating in x2APIC mode, 32-
bit APIC ID can be read by executing a RDMSR instruction to read the
processor’s x2APIC ID register. This method is equivalent to executing CPUID
leaf 0BH described below.
— If the local APIC unit is operating in xAPIC mode, 8-bit APIC ID can be read by
executing a MOV instruction to read the processor’s local APIC ID register
(see Section 10.4.6, “Local APIC ID”). This is the ID to use for directing
physical destination mode interrupts to the processor.
• Read ACPI or MP table — As part of the MP initialization protocol, the BIOS
creates an ACPI table and an MP table. These tables are defined in the Multipro-
cessor Specification Version 1.4 and provide software with a list of the processors
in the system and their local APIC IDs. The format of the ACPI table is derived
from the ACPI specification, which is an industry standard power management
and platform configuration specification for MP systems.
• Read Initial APIC ID (If the process does not support CPUID leaf 0BH) — An
APIC ID is assigned to a logical processor during power up. This is the initial APIC
ID reported by CPUID.1:EBX[31:24] and may be different from the current value
read from the local APIC. The initial APIC ID can be used to determine the
topological relationship between logical processors for multi-processor systems
that do not support CPUID leaf 0BH.
Bits in the 8-bit initial APIC ID can be interpreted using several bit masks. Each
bit mask can be used to extract an identifier to represent a hierarchical level of
the multi-threading resource topology in an MP system (See Section 8.9.1,
“Hierarchical Mapping of Shared Resources”). The initial APIC ID may consist of
up to four bit-fields. In a non-clustered MP system, the field consists of up to
three bit fields.
• Read 32-bit APIC ID from CPUID leaf 0BH (If the processor supports CPUID
leaf 0BH) — A unique APIC ID is assigned to a logical processor during power up.
This APIC ID is reported by CPUID.0BH:EDX[31:0] as a 32-bit value. Use the 32-
bit APIC ID and CPUID leaf 0BH to determine the topological relationship between
logical processors if the processor supports CPUID leaf 0BH.
Bits in the 32-bit x2APIC ID can be extracted into sub-fields using CPUID leaf 0BH
parameters. (See Section 8.9.1, “Hierarchical Mapping of Shared Resources”).
Figure 8-2 shows two examples of APIC ID bit fields in earlier single-core processors.
In single-core Intel Xeon processors, the APIC ID assigned to a logical processor