Filter
Top Products
Vol. 3 10-21
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
10.5.1.3 Reserved Bit Checking
Section 10.5.1.2 and Table 10-3 specifies the reserved bit definitions for the APIC
registers in x2APIC mode. Non-zero writes (by WRMSR instruction) to reserved bits
to these registers will raise a general protection fault exception while reads return
zeros (RsvdZ semantics).
In x2APIC mode, the local APIC ID register is increased to 32 bits wide. This enables
2^32 -1 processors to be addressable in physical destination mode. This 32-bit value
is referred to as “x2APIC ID”. A processor implementation may choose to support less
than 32 bits in its hardware. System software should be agnostic to the actual
number of bits that are implemented. All non-implemented bits will return zeros on
reads by software.
The APIC ID value of FFFF_FFFFH and the highest value corresponding to the imple-
mented bit-width of the local APIC ID register in the system are reserved and cannot
be assigned to any logical processor.
In x2APIC mode, the local APIC ID register is a read-only register to system software
and will be initialized by hardware. It is accessed via the RDMSR instruction reading
the MSR at address 0802H.
Each logical processor in the system (including clusters with a communication fabric)
must be configured with an unique x2APIC ID to avoid collisions of x2APIC IDs. On
DP and high-end MP processors targeted to specific market segments and depending
on the system configuration, it is possible that logical processors in different and "un-
connected" clusters power up initialized with overlapping x2APIC IDs. In these
configurations, a model-specific means may be provided in those product segments
03E0H 03EH Divide Configuration
Register (for Timer)
Read/Write.
Not supported 03FH SELF IPI
4
Write only Only in x2APIC mode
040H-3FFH Reserved
NOTES:
1. Destination format register (DFR) is supported in xAPIC mode at
MMIO offset 00E0H.
2. APIC register at MMIO offset 0310H is accessible in xAPIC mode
only
3. MSR 831H (offset 31H) is reserved; read/write operations will result
in a GP fault.
4. SELF IPI register is supported only if x2APIC mode is enabled.
Table 10-3. Local APIC Register Address Map Supported by x2APIC (Contd.)
MMIO Offset
(xAPIC mode)
MSR Offset
(x2APIC
mode) Register Name
R/W
Semantics Comments