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Vol. 3 11-29
MEMORY CACHE CONTROL
11.9 INVALIDATING THE TRANSLATION LOOKASIDE
BUFFERS (TLBS)
The processor updates its address translation caches (TLBs) transparently to soft-
ware. Several mechanisms are available, however, that allow software and hardware
to invalidate the TLBs either explicitly or as a side effect of another operation. Most
details are given in
Section 4.10.3, “Invalidation of TLBs and Paging-Structure
Caches.” In addition, the following operations invalidate all TLB entries, irrespective
of the setting of the G flag:
• Asserting or de-asserting the FLUSH# pin.
• (Pentium 4, Intel Xeon, and later processors only.) Writing to an MTRR (with a
WRMSR instruction).
• Writing to control register CR0 to modify the PG or PE flag.
• (Pentium 4, Intel Xeon, and later processors only.) Writing to control register CR4
to modify the PSE, PGE, or PAE flag.
See Section 4.10, “Caching Translation Information,” for additional information about
the TLBs.
11.10 STORE BUFFER
Intel 64 and IA-32 processors temporarily store each write (store) to memory in a
store buffer. The store buffer improves processor performance by allowing the
processor to continue executing instructions without having to wait until a write to
memory and/or to a cache is complete. It also allows writes to be delayed for more
efficient use of memory-access bus cycles.
In general, the existence of the store buffer is transparent to software, even in
systems that use multiple processors. The processor ensures that write operations
are always carried out in program order. It also insures that the contents of the store
buffer are always drained to memory in the following situations:
• When an exception or interrupt is generated.
• (P6 and more recent processor families only) When a serializing instruction is
executed.
• When an I/O instruction is executed.
• When a LOCK operation is performed.
• (P6 and more recent processor families only) When a BINIT operation is
performed.
• (Pentium III, and more recent processor families only) When using an SFENCE
instruction to order stores.
• (Pentium 4 and more recent processor families only) When using an MFENCE
instruction to order stores.