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Vol. 3 6-5
INTERRUPT AND EXCEPTION HANDLING
defined interrupt vectors from 0 through 255; those that can be delivered through
the local APIC include interrupt vectors 16 through 255.
The IF flag in the EFLAGS register permits all maskable hardware interrupts to be
masked as a group (see Section 6.8.1, “Masking Maskable Hardware Interrupts”).
Note that when interrupts 0 through 15 are delivered through the local APIC, the
APIC indicates the receipt of an illegal vector.
6.3.3 Software-Generated Interrupts
The INT n instruction permits interrupts to be generated from within software by
supplying an interrupt vector number as an operand. For example, the INT 35
instruction forces an implicit call to the interrupt handler for interrupt 35.
Any of the interrupt vectors from 0 to 255 can be used as a parameter in this instruc-
tion. If the processor’s predefined NMI vector is used, however, the response of the
processor will not be the same as it would be from an NMI interrupt generated in the
normal manner. If vector number 2 (the NMI vector) is used in this instruction, the
NMI interrupt handler is called, but the processor’s NMI-handling hardware is not
activated.
Interrupts generated in software with the INT n instruction cannot be masked by the
IF flag in the EFLAGS register.
6.4 SOURCES OF EXCEPTIONS
The processor receives exceptions from three sources:
• Processor-detected program-error exceptions.
• Software-generated exceptions.
• Machine-check exceptions.
6.4.1 Program-Error Exceptions
The processor generates one or more exceptions when it detects program errors
during the execution in an application program or the operating system or executive.
Intel 64 and IA-32 architectures define a vector number for each processor-detect
-
able exception. Exceptions are classified as faults, traps, and aborts (see Section
6.5, “Exception Classifications”).