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2-28 Vol. 3
SYSTEM ARCHITECTURE OVERVIEW
SLDT Store LDT Register No No
LGDT Load GDT Register No Yes
SGDT Store GDT Register No No
LTR Load Task Register No Yes
STR Store Task Register No No
LIDT Load IDT Register No Yes
SIDT Store IDT Register No No
MOV CRn Load and store control registers No Yes
SMSW Store MSW Yes No
LMSW Load MSW No Yes
CLTS Clear TS flag in CR0 No Yes
ARPL Adjust RPL Yes
1, 5
No
LAR Load Access Rights Yes No
LSL Load Segment Limit Yes No
VERR Verify for Reading Yes No
VERW Verify for Writing Yes No
MOV DRn Load and store debug registers No Yes
INVD Invalidate cache, no writeback No Yes
WBINVD Invalidate cache, with writeback No Yes
INVLPG Invalidate TLB entry No Yes
HLT Halt Processor No Yes
LOCK (Prefix) Bus Lock Yes No
RSM Return from system management
mode
No Yes
RDMSR
3
Read Model-Specific Registers No Yes
WRMSR
3
Write Model-Specific Registers No Yes
RDPMC
4
Read Performance-Monitoring
Counter
Yes Yes
2
RDTSC
3
Read Time-Stamp Counter Yes Yes
2
RDTSCP
7
Read Serialized Time-Stamp Counter Yes Yes
2
Table 2-2. Summary of System Instructions (Contd.)
Instruction
Description
Useful to
Application?
Protected from
Application?