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19-12 Vol. 3
ARCHITECTURE COMPATIBILITY
Software written to run on a 16-bit IA-32 math coprocessor may not operate
correctly on a 16-bit x87 FPU, if it uses the FLDENV, FRSTOR, or FXRSTOR instruc-
tions to change tags to values (other than to empty) that are different from actual
register contents.
The encoding in the tag word for the 32-bit x87 FPUs for unsupported data formats
(including pseudo-zero and unnormal) is special (10B), to comply with IEEE Standard
754. The encoding in the 16-bit IA-32 math coprocessors for pseudo-zero and
unnormal is valid (00B) and the encoding for other unsupported data formats is
special (10B). Code that recognizes the pseudo-zero or unnormal format as valid
must therefore be changed if it is ported to a 32-bit x87 FPU.
19.18.5 Data Types
This section discusses the differences of data types for the various x87 FPUs and
math coprocessors.
19.18.5.1 NaNs
The 32-bit x87 FPUs distinguish between signaling NaNs (SNaNs) and quiet NaNs
(QNaNs). These x87 FPUs only generate QNaNs and normally do not generate an
exception upon encountering a QNaN. An invalid-operation exception (#I) is gener
-
ated only upon encountering a SNaN, except for the FCOM, FIST, and FBSTP instruc-
tions, which also generates an invalid-operation exceptions for a QNaNs. This
behavior matches IEEE Standard 754.
The 16-bit IA-32 math coprocessors only generate one kind of NaN (the equivalent of
a QNaN), but the raise an invalid-operation exception upon encountering any kind of
NaN.
When porting software written to run on a 16-bit IA-32 math coprocessor to a 32-bit
x87 FPU, uninitialized memory locations that contain QNaNs should be changed to
SNaNs to cause the x87 FPU or math coprocessor to fault when uninitialized memory
locations are referenced.
19.18.5.2 Pseudo-zero, Pseudo-NaN, Pseudo-infinity, and Unnormal
Formats
The 32-bit x87 FPUs neither generate nor support the pseudo-zero, pseudo-NaN,
pseudo-infinity, and unnormal formats. Whenever they encounter them in an arith-
metic operation, they raise an invalid-operation exception. The 16-bit IA-32 math
coprocessors define and support special handling for these formats. Support for
these formats was dropped to conform with IEEE Standard 754 for Binary Floating-
Point Arithmetic.
This change should not impact software ported from 16-bit IA-32 math coprocessors
to 32-bit x87 FPUs. The 32-bit x87 FPUs do not generate these formats, and there-
fore will not encounter them unless software explicitly loads them in the data regis-