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Vol. 3 4-15
PAGING
those that do neither because they are “not present”; bit 0 (P) and bit 7 (PS) are
highlighted because they determine how such an entry is used.
4.4 PAE PAGING
A logical processor uses PAE paging if CR0.PG = 1, CR4.PAE = 1, and
IA32_EFER.LME = 0. PAE paging translates 32-bit linear addresses to 52-bit physical
addresses.
1
Although 52 bits corresponds to 4 PBytes, linear addresses are limited to
32 bits; at most 4 GBytes of linear-address space may be accessed at any given time.
With PAE paging, a logical processor maintains a set of four (4) PDPTE registers,
which are loaded from an address in CR3. Linear address are translated using 4 hier-
archies of in-memory paging structures, each located using one of the PDPTE regis-
31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0
Address of page directory
1
NOTES:
1. CR3 has 64 bits on processors supporting the Intel-64 architecture. These bits are ignored with
32-bit paging.
Ignored
P
C
D
P
W
T
Ignored CR3
Bits 31:22 of address
of 2MB page frame
Reserved
(must be 0)
Bits 39:32
of
address
2
2. This example illustrates a processor in which MAXPHYADDR is 36. If this value is larger or smaller,
the number of bits reserved in positions 20:13 of a PDE mapping a 4-MByte will change.
P
A
T
Ignored G 1 DA
P
C
D
P
W
T
U
/
S
R
/
W
1
PDE:
4MB
page
Address of page table Ignored 0
I
g
n
A
P
C
D
P
W
T
U
/
S
R
/
W
1
PDE:
page
table
Ignored 0
PDE:
not
present
Address of 4KB page frame Ignored G
P
A
T
DA
P
C
D
P
W
T
U
/
S
R
/
W
1
PTE:
4KB
page
Ignored 0
PTE:
not
present
Figure 4-4. Formats of CR3 and Paging-Structure Entries with 32-Bit Paging
1. If MAXPHYADDR < 52, bits in the range 51:MAXPHYADDR will be 0 in any physical address used
by PAE paging. (The corresponding bits are reserved in the paging-structure entries.) See Section
4.1.4 for how to determine MAXPHYADDR.