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Vol. 3 15-7
MACHINE-CHECK ARCHITECTURE
encoding of 06H_1AH and onward): the operating system or
executive software must not modify the contents of the
IA32_MC0_CTL MSR. This MSR is internally aliased to the
EBL_CR_POWERON MSR and controls platform-specific error
handling features. System specific firmware (the BIOS) is responsible
for the appropriate initialization of the IA32_MC0_CTL MSR. P6 family
processors only allow the writing of all 1s or all 0s to the
IA32_MCi_CTL MSR.
15.3.2.2 IA32_MCi_STATUS MSRS
Each IA32_MCi_STATUS MSR contains information related to a machine-
check error if its VAL (valid) flag is set (see
Figure 15-5). Software is respon-
sible for clearing IA32_MCi_STATUS MSRs by explicitly writing 0s to them;
writing 1s to them causes a general-protection exception.
NOTE
Figure 15-5 depicts the IA32_MCi_STATUS MSR when
IA32_MCG_CAP[24] = 1, IA32_MCG_CAP[11] = 1 and
IA32_MCG_CAP[10] = 1. When IA32_MCG_CAP[24] = 0 and
IA32_MCG_CAP[11] = 1, bits 56:55 is reserved and bits 54:53 for
threshold-based error reporting. When IA32_MCG_CAP[11] = 0, bits
56:53 are part of the “Other Information” field. The use of bits 54:53
for threshold-based error reporting began with Intel Core Duo
processors, and is currently used for cache memory. See
Section
15.4, “Enhanced Cache Error reporting,” for more information. When
IA32_MCG_CAP[10] = 0, bits 52:38 are part of the “Other Infor-
mation” field. The use of bits 52:38 for corrected MC error count is