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Vol. 3 10-33
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
Interrupt Input Pin Polarity
Specifies the polarity of the corresponding interrupt pin: (0)
active high or (1) active low.
Remote IRR Flag (Read Only)
For fixed mode, level-triggered interrupts; this flag is set when
the local APIC accepts the interrupt for servicing and is reset
when an EOI command is received from the processor. The
meaning of this flag is undefined for edge-triggered interrupts
and other delivery modes.
Trigger Mode Selects the trigger mode for the local LINT0 and LINT1 pins: (0)
edge sensitive and (1) level sensitive. This flag is only used
when the delivery mode is Fixed. When the delivery mode is
NMI, SMI, or INIT, the trigger mode is always edge sensitive.
When the delivery mode is ExtINT, the trigger mode is always
level sensitive. The timer and error interrupts are always treated
as edge sensitive.
If the local APIC is not used in conjunction with an I/O APIC and
fixed delivery mode is selected; the Pentium 4, Intel Xeon, and
P6 family processors will always use level-sensitive triggering,
regardless if edge-sensitive triggering is selected.
Mask Interrupt mask: (0) enables reception of the interrupt and (1)
inhibits reception of the interrupt. When the local APIC handles
a performance-monitoring counters interrupt, it automatically
sets the mask flag in the corresponding LVT entry. This flag will
remain set until software clears it.
Timer Mode Selects the timer mode: (0) one-shot and (1) periodic (see
Section 10.6.4, “APIC Timer”).
10.6.2 Valid Interrupt Vectors
The Intel 64 and IA-32 architectures define 256 vector numbers, ranging from 0
through 255 (see
Section 6.2, “Exception and Interrupt Vectors”). Local and I/O
APICs support 240 of these vectors (in the range of 16 to 255) as valid interrupts.
When an interrupt vector in the range of 0 to 15 is sent or received through the local
APIC, the APIC indicates an illegal vector in its Error Status Register (see
Section
10.6.3, “Error Handling”). The Intel 64 and IA-32 architectures reserve vectors 16
through 31 for predefined interrupts, exceptions, and Intel-reserved encodings (see
Table 6-1). However, the local APIC does not treat vectors in this range as illegal.
When an illegal vector value (0 to 15) is written to an LVT entry and the delivery
mode is Fixed (bits 8-11
equal 0), the APIC may signal an illegal vector error, without
regard to whether the mask bit is set or whether an interrupt is actually seen on the
input.