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11-4 Vol. 3
MEMORY CACHE CONTROL
Instruction TLB
(4-KByte Pages)
• Pentium 4 and Intel Xeon processors (Based on Intel NetBurst
microarchitecture): 128 entries, 4-way set associative.
• Intel Atom processors: 32-entries, fully associative.
• Intel Core i7 processor: 64-entries per thread (128-entries per core), 4-
way set associative.
• Intel Core 2 Duo, Intel Core Duo, Intel Core Solo processors, Pentium M
processor: 128 entries, 4-way set associative.
• P6 family processors: 32 entries, 4-way set associative.
• Pentium processor: 32 entries, 4-way set associative; fully set
associative for Pentium processors with MMX technology.
Data TLB (4-KByte
Pages)
• Intel Core i7 processor, DTLB0: 64-entries, 4-way set associative.
• Intel Core 2 Duo processors: DTLB0, 16 entries, DTLB1, 256 entries, 4
ways.
• Intel Atom processors: 16-entry-per-thread micro-TLB, fully associative;
64-entry DTLB, 4-way set associative; 16-entry PDE cache, fully
associative.
• Pentium 4 and Intel Xeon processors (Based on Intel NetBurst
microarchitecture): 64 entry, fully set associative, shared with large page
DTLB.
• Intel Core Duo, Intel Core Solo processors, Pentium M processor: 128
entries, 4-way set associative.
• Pentium and P6 family processors: 64 entries, 4-way set associative;
fully set, associative for Pentium processors with MMX technology.
Instruction TLB
(Large Pages)
• Intel Core i7 processor: 7-entries per thread, fully associative.
• Intel Core 2 Duo processors: 4 entries, 4 ways.
• Pentium 4 and Intel Xeon processors: large pages are fragmented.
• Intel Core Duo, Intel Core Solo, Pentium M processor: 2 entries, fully
associative.
• P6 family processors: 2 entries, fully associative.
• Pentium processor: Uses same TLB as used for 4-KByte pages.
Data TLB (Large
Pages)
• Intel Core i7 processor, DTLB0: 32-entries, 4-way set associative.
• Intel Core 2 Duo processors: DTLB0, 16 entries, DTLB1, 32 entries, 4
ways.
• Intel Atom processors: 8 entries, 4-way set associative.
• Pentium 4 and Intel Xeon processors: 64 entries, fully set associative;
shared with small page data TLBs.
• Intel Core Duo, Intel Core Solo, Pentium M processor: 8 entries, fully
associative.
• P6 family processors: 8 entries, 4-way set associative.
• Pentium processor: 8 entries, 4-way set associative; uses same TLB as
used for 4-KByte pages in Pentium processors with MMX technology.
Second-level Unified
TLB (4-KByte
Pages)
• Intel Core i7 processor, STLB: 512-entries, 4-way set associative.
Table 11-1. Characteristics of the Caches, TLBs, Store Buffer, and
Write Combining Buffer in Intel 64 and IA-32 Processors (Contd.)
Cache or Buffer Characteristics