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Vol. 3 15-21
MACHINE-CHECK ARCHITECTURE
• Delivery status, bits 12 — It is a read-only bit that, when set, indicates that an
interrupt from this source has been delivered to the processor core, but has not
yet been accepted.
• Mask, bits 16 — When set, inhibits reception of the interrupt. (Unlike the
PerfMon LVT entry, this bit is not set when an interrupt is received. When clear,
CMCI is not masked. The mask bit is set by default.
• Bits 31:17, 15:13 and 11 are reserved.
15.5.2 System Software Recommendation for Managing CMCI and
Machine Check Resources
System software must enable and manage CMCI, set up interrupt handlers
to service CMCI interrupts delivered to affected logical processors, program
CMCI LVT entry, and query machine check banks that are shared by more
than one logical processors.
This section describes techniques system software can implement to
manage CMCI initialization, service CMCI interrupts in a efficient manner to
minimize contentions to access shared MSR resources.
15.5.2.1 CMCI Initialization
Although a CMCI interrupt may be delivered to more than one logical proces-
sors depending on the nature of the corrected MC error, only one instance of
the interrupt service routine needs to perform the necessary service and
make queries to the machine-check banks. The following steps describes a
technique that limits the amount of work the system has to do in response to
a CMCI.
• To provide maximum flexibility, system software should define per-thread data
structure for each logical processor to allow equal-opportunity and efficient
response to interrupt delivery. Specifically, the per-thread data structure should
include a set of per-bank fields to track which machine check bank it needs to
access in response to a delivered CMCI interrupt. The number of banks that
needs to be tracked is determined by
IA32_MCG_CAP[7:0].
• Initialization of per-thread data structure. The initialization of per-thread data
structure must be done serially on each logical processor in the system. The
sequencing order to start the per-thread initialization between different logical
processor is arbitrary. But it must observe the following specific detail to satisfy
the shared nature of specific MSR resources:
a. Each thread initializes its data structure to indicate that it does not own any
MC bank registers.