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Vol. 3 10-47
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
APICs to be addressed on the APIC bus. A broadcast to all local APICs is specified with
0FH.
NOTE
The number of local APICs that can be addressed on the system bus
may be restricted by hardware.
10.7.2.2 Logical Destination Mode
In logical destination mode, IPI destination is specified using an 8-bit message desti-
nation address (MDA), which is entered in the destination field of the ICR. Upon
receiving an IPI message that was sent using logical destination mode, a local APIC
compares the MDA in the message with the values in its LDR and DFR to determine if
it should accept and handle the IPI. For both configurations of logical destination
mode, when combined with lowest priority delivery mode, software is responsible for
ensuring that all of the local APICs included in or addressed by the IPI or I/O
subsystem interrupt are present and enabled to receive the interrupt.
Figure 10-19 shows the layout of the logical destination register (LDR). The 8-bit
logical APIC ID field in this register is used to create an identifier that can be
compared with the MDA.
NOTE
The logical APIC ID should not be confused with the local APIC ID that
is contained in the local APIC ID register.
Figure 10-20 shows the layout of the destination format register (DFR). The 4-bit
model field in this register selects one of two models (flat or cluster) that can be used
to interpret the MDA when using logical destination mode.
Figure 10-19. Logical Destination Register (LDR)
31
0
2324
ReservedLogical APIC ID
Address: 0FEE0 00D0H
Value after reset: 0000 0000H