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4-50 Vol. 3
PAGING
TLB shootdown algorithm for processors supporting the Intel-64 and IA-32 architec-
tures:
1. Begin barrier: Stop all but one logical processor; that is, cause all but one to
execute the HLT instruction or to enter a spin loop.
2. Allow the active logical processor to change the necessary paging-structure
entries.
3. Allow all logical processors to perform invalidations appropriate to the modifica-
tions to the paging-structure entries.
4. Allow all logical processors to resume normal operation.
Alternative, performance-optimized, TLB shootdown algorithms may be developed;
however, software developers must take care to ensure that the following conditions
are met:
• All logical processors that are using the paging structures that are being modified
must participate and perform appropriate invalidations after the modifications
are made.
• If the modifications to the paging-structure entries are made before the barrier
or if there is no barrier, the operating system must ensure one of the following:
(1) that the affected linear-address range is not used between the time of modifi-
cation and the time of invalidation; or (2) that it is prepared to deal with the
consequences of the affected linear-address range being used during that period.
For example, if the operating system does not allow pages being freed to be
reallocated for another purpose until after the required invalidations, writes to
those pages by errant software will not unexpectedly modify memory that is in
use.
• Software must be prepared to deal with reads, instruction fetches, and prefetch
requests to the affected linear-address range that are a result of speculative
execution that would never actually occur in the executed code path.
When multiple logical processors are using the same linear-address space at the
same time, they must coordinate before any request to modify the paging-structure
entries that control that linear-address space. In these cases, the barrier in the TLB
shootdown routine may not be required. For example, when freeing a range of linear
addresses, some other mechanism can assure no logical processor is using that
range before the request to free it is made. In this case, a logical processor freeing
the range can clear the P flags in the PTEs associated with the range, free the phys-
ical page frames associated with the range, and then signal the other logical proces-
sors using that linear-address space to perform the necessary invalidations. All the
affected logical processors must complete their invalidations before the linear-
address range and the physical page frames previously associated with that range
can be reallocated.