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13-8 Vol. 3
SYSTEM PROGRAMMING FOR INSTRUCTION SET EXTENSIONS AND PROCESSOR
13.1.6.1 Numeric Error flag and IGNNE#
SSE/SSE2/SSE3/SSE4 extensions ignore the NE flag in control register CR0 (that is,
treats it as if it were always set) and the IGNNE# pin. When an unmasked SIMD
floating-point exception is detected, it is always reported by generating a SIMD
floating-point exception (#XM).
13.2 EMULATION OF SSE/SSE2/SSE3/SSSE3/SSE4
EXTENSIONS
The Intel 64 and IA-32 architecture does not support emulation of the
SSE/SSE2/SSE3/SSSE3/SSE4 instructions, as they do for x87 FPU instructions.
The EM flag in control register CR0 (provided to invoke emulation of x87 FPU instruc-
tions) cannot be used to invoke emulation of SSE/SSE2/SSE3/SSSE3/SSE4 instruc-
tions. If an SSE/SSE2/SSE3/SSSE3/SSE4 instruction is executed when CR0.EM = 1,
an invalid opcode exception (#UD) is generated. See Table 13-1.
13.3 SAVING AND RESTORING THE
SSE/SSE2/SSE3/SSSE3/SSE4 STATE
The SSE/SSE2/SSE3/SSSE3/SSE4 state consists of the state of the XMM and MXCSR
registers. The recommended method for saving and restoring this state follows:
• Execute an FXSAVE instruction to save the state of the XMM and MXCSR registers
to memory.
• Execute an FXRSTOR instruction to restore the state of the XMM and MXCSR
registers from the image saved in memory by the FXSAVE instruction.
This save and restore method is required for all operating systems. See Section 13.5,
“Designing OS Facilities for AUTOMATICALLY Saving x87 FPU, MMX, and
SSE/SSE2/SSE3/SSSE3/SSE4 state on Task or Context Switches.”
In some cases, applications can only save the XMM and MXCSR registers in the
following way:
• Execute MOVDQ instructions to save the contents of each XMM registers to
memory.
• Execute a STMXCSR instruction to save the state of the MXCSR register to
memory.
In some cases, applications can only restore the XMM and MXCSR registers in the
following way:
• Execute MOVDQ instructions to read the saved contents of each XMM registers
from memory to XMM registers.