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Vol. 3A xxxix
CONTENTS
PAGE
Table 8-2. Initial APIC IDs for the Logical Processors in a System that has Two Physical
Processors Supporting Dual-Core and Intel Hyper-Threading Technology8-53
Table 8-3. Example of Possible x2APIC ID Assignment in a System that has Two Physical
Processors Supporting x2APIC and Intel Hyper-Threading Technology8-53
Table 9-1. IA-32 Processor States Following Power-up, Reset, or INIT . . . . . . . . . . . . . . . . . . . . .9-2
Table 9-2. Recommended Settings of EM and MP Flags on IA-32 Processors . . . . . . . . . . . . . . . 9-7
Table 9-3. Software Emulation Settings of EM, MP, and NE Flags . . . . . . . . . . . . . . . . . . . . . . . . . .9-8
Table 9-4. Main Initialization Steps in STARTUP.ASM Source Listing . . . . . . . . . . . . . . . . . . . . . .9-21
Table 9-5. Relationship Between BLD Item and ASM Source File. . . . . . . . . . . . . . . . . . . . . . . . . .9-35
Table 9-6. Microcode Update Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-38
Table 9-7. Microcode Update Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-40
Table 9-8. Extended Processor Signature Table Header Structure. . . . . . . . . . . . . . . . . . . . . . . .9-41
Table 9-9. Processor Signature Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-41
Table 9-10. Processor Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-43
Table 9-11. Microcode Update Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-48
Table 9-12. Microcode Update Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-55
Table 9-13. Parameters for the Presence Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-56
Table 9-14. Parameters for the Write Update Data Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-57
Table 9-15. Parameters for the Control Update Sub-function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-62
Table 9-17. Parameters for the Read Microcode Update Data Function . . . . . . . . . . . . . . . . . . . .9-63
Table 9-16. Mnemonic Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-63
Table 9-18. Return Code Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-65
Table 10-1 Local APIC Register Address Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-8
Table 10-2. x2APIC Operating Mode Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17
Table 10-3. Local APIC Register Address Map Supported by x2APIC. . . . . . . . . . . . . . . . . . . . . . 10-18
Table 10-4. MSR/MMIO Interface of a Local x2APIC in Different Modes of Operation . . . . . . 10-22
Table 10-5. ESR Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-35
Table 10-6 Valid Combinations for the Pentium 4 and Intel Xeon Processors’
Local xAPIC Interrupt Command Register10-42
Table 10-7 Valid Combinations for the P6 Family Processors’
Local APIC Interrupt Command Register10-43
Table 11-1. Characteristics of the Caches, TLBs, Store Buffer, and
Write Combining Buffer in Intel 64 and IA-32 Processors11-2
Table 11-2. Memory Types and Their Properties. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-9
Table 11-3. Methods of Caching Available in Intel Core 2 Duo, Intel Atom, Intel Core Duo, Pentium
M, Pentium 4, Intel Xeon, P6 Family, and Pentium Processors11-10
Table 11-4. MESI Cache Line States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14
Table 11-5. Cache Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-17
Table 11-6. Effective Page-Level Memory Type for Pentium Pro and
Pentium II Processors11-21
Table 11-7. Effective Page-Level Memory Types for Pentium III and More Recent Processor
Families11-22
Table 11-8. Memory Types That Can Be Encoded in MTRRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-30
Table 11-9. Address Mapping for Fixed-Range MTRRs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-35
Table 11-10. Memory Types That Can Be Encoded With PAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-49
Table 11-11. Selection of PAT Entries with PAT, PCD, and PWT Flags . . . . . . . . . . . . . . . . . . . . . 11-50
Table 11-12. Memory Type Setting of PAT Entries Following a Power-up or Reset. . . . . . . . . 11-50
Table 12-1. Action Taken By MMX Instructions
for Different Combinations of EM, MP and TS12-1
Table 12-2. Effects of MMX Instructions on x87 FPU State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-3
Table 12-3. Effect of the MMX, x87 FPU, and FXSAVE/FXRSTOR Instructions on the
x87 FPU Tag Word12-4