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Vol. 3 15-45
MACHINE-CHECK ARCHITECTURE
was corrected (UC=0) or uncorrected (UC=1). The MCE handler can optionally
log and clear the corrected errors in the MC banks if it can implement software
algorithm to avoid the undesired race conditions with the CMCI or CMC polling
handler.
• For uncorrectable errors, the EIPV flag in the IA32_MCG_STATUS register
indicates (when set) that the instruction pointed to by the instruction pointer
pushed onto the stack when the machine-check exception is generated is directly
associated with the error. When this flag is cleared, the instruction pointed to
may not be associated with the error.
• The MCIP flag in the IA32_MCG_STATUS register indicates whether a machine-
check exception was generated. When a machine check exception is generated,
it is expected that the MCIP flag in the IA32_MCG_STATUS register is set to 1. If
it is not set, this machine check was generated by either an INT 18 instruction or
some piece of hardware signaling an interrupt with vector 18.
When IA32_MCG_CAP [24] is 1, the following rules can apply when writing a
machine check exception (MCE) handler to support software recovery:
• The PCC flag in each IA32_MCi_STATUS register indicates whether recovery from
the error is possible for uncorrected errors (UC=1). If the PCC flag is set for
uncorrected errors (UC=1), recovery is not possible. When recovery is not
possible, the MCE handler typically records the error information and signals the
operating system to reset the system.
• The RIPV flag in the IA32_MCG_STATUS register indicates whether restarting the
program execution from the instruction pointer saved on the stack for the
machine check exception is possible. When the RIPV is set, program execution
can be restarted reliably when recovery is possible. If the RIPV flag is not set,
program execution cannot be restarted reliably. In this case the recovery
algorithm may involve terminating the current program execution and resuming
an alternate thread of execution upon return from the machine check handler
when recovery is possible. When recovery is not possible, the MCE handler
signals the operating system to reset the system.
• When the EN flag is zero but the VAL and UC flags are one in the
IA32_MCi_STATUS register, the reported uncorrected error in this bank is not
enabled. As uncorrected errors with the EN flag = 0 are not the source of
machine check exceptions, the MCE handler should log and clear non-enabled
errors when the S bit is set and should continue searching for enabled errors from
the other IA32_MCi_STATUS registers. Note that when IA32_MCG_CAP [24] is 0,
any uncorrected error condition (VAL =1 and UC=1) including the one with the
EN flag cleared are fatal and the handler must signal the operating system to
reset the system. For the errors that do not generate machine check exceptions,
the EN flag has no meaning. See Appendix A: Table A-4 to find the errors that do
not generate machine check exceptions.
• When the VAL flag is one, the UC flag is one, the EN flag is one and the PCC flag
is zero in the IA32_MCi_STATUS register, the error in this bank is an uncorrected
recoverable (UCR) error. The MCE handler needs to examine the S flag and the