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19-24 Vol. 3
ARCHITECTURE COMPATIBILITY
19.21 CONTROL REGISTERS
The following sections identify the new control registers and control register flags
and fields that were introduced to the 32-bit IA-32 in various processor families. See
Figure 2-6 for the location of these flags and fields in the control registers.
The Pentium III processor introduced one new control flag in control register CR4:
• OSXMMEXCPT (bit 10) — The OS will set this bit if it supports unmasked SIMD
floating-point exceptions.
The Pentium II processor introduced one new control flag in control register CR4:
• OSFXSR (bit 9) — The OS supports saving and restoring the Pentium III processor
state during context switches.
The Pentium Pro processor introduced three new control flags in control register CR4:
• PAE (bit 5) — Physical address extension. Enables paging mechanism to
reference extended physical addresses when set; restricts physical addresses to
32 bits when clear (see also:
Section 19.22.1.1, “Physical Memory Addressing
Extension”).
• PGE (bit 7) — Page global enable. Inhibits flushing of frequently-used or shared
pages on CR3 writes (see also: Section 19.22.1.2, “Global Pages”).
• PCE (bit 8) — Performance-monitoring counter enable. Enables execution of the
RDPMC instruction at any protection level.
The content of CR4 is 0H following a hardware reset.
Control register CR4 was introduced in the Pentium processor. This register contains
flags that enable certain new extensions provided in the Pentium processor:
• VME — Virtual-8086 mode extensions. Enables support for a virtual interrupt flag
in virtual-8086 mode (see
Section 17.3, “Interrupt and Exception Handling in
Virtual-8086 Mode”).
• PVI — Protected-mode virtual interrupts. Enables support for a virtual interrupt
flag in protected mode (see
Section 17.4, “Protected-Mode Virtual Interrupts”).
• TSD — Time-stamp disable. Restricts the execution of the RDTSC instruction to
procedures running at privileged level 0.
• DE — Debugging extensions. Causes an undefined opcode (#UD) exception to be
generated when debug registers DR4 and DR5 are references for improved
performance (see
Section 19.23.3, “Debug Registers DR4 and DR5”).
• PSE — Page size extensions. Enables 4-MByte pages with 32-bit paging when set
(see
Section 4.3, “32-Bit Paging”).
• MCE — Machine-check enable. Enables the machine-check exception, allowing
exception handling for certain hardware error conditions (see Chapter 15,
“Machine-Check Architecture”).
The Intel486 processor introduced five new flags in control register CR0: