Filter
Top Products
Vol. 3 19-25
ARCHITECTURE COMPATIBILITY
• NE — Numeric error. Enables the normal mechanism for reporting floating-point
numeric errors.
• WP — Write protect. Write-protects read-only pages against supervisor-mode
accesses.
• AM — Alignment mask. Controls whether alignment checking is performed.
Operates in conjunction with the AC (Alignment Check) flag.
• NW — Not write-through. Enables write-throughs and cache invalidation cycles
when clear and disables invalidation cycles and write-throughs that hit in the
cache when set.
• CD — Cache disable. Enables the internal cache when clear and disables the
cache when set.
The Intel486 processor introduced two new flags in control register CR3:
• PCD — Page-level cache disable. The state of this flag is driven on the PCD# pin
during bus cycles that are not paged, such as interrupt acknowledge cycles, when
paging is enabled. The PCD# pin is used to control caching in an external cache
on a cycle-by-cycle basis.
• PWT — Page-level write-through. The state of this flag is driven on the PWT# pin
during bus cycles that are not paged, such as interrupt acknowledge cycles, when
paging is enabled. The PWT# pin is used to control write through in an external
cache on a cycle-by-cycle basis.
19.22 MEMORY MANAGEMENT FACILITIES
The following sections describe the new memory management facilities available in
the various IA-32 processors and some compatibility differences.
19.22.1 New Memory Management Control Flags
The Pentium Pro processor introduced three new memory management features:
physical memory addressing extension, the global bit in page-table entries, and
general support for larger page sizes. These features are only available when oper-
ating in protected mode.
19.22.1.1 Physical Memory Addressing Extension
The new PAE (physical address extension) flag in control register CR4, bit 5, may
enable additional address lines on the processor, allowing extended physical
addresses. This option can only be used when paging is enabled, using a new page-
table mechanism provided to support the larger physical address range (see
Section
4.1, “Paging Modes and Control Bits”).