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4-30 Vol. 3
PAGING
comprises 512 64-bit entries (PTEs). A PTE is selected using the physical address
defined as follows:
— Bits 51:12 are from the PDE.
— Bits 11:3 are bits 20:12 of the linear address.
— Bits 2:0 are all 0.
• Because a PTE is identified using bits 47:12 of the linear address, every PTE
maps a 4-KByte page (see Table 4-17). The final physical address is computed as
follows:
— Bits 51:12 are from the PTE.
Table 4-16. Format of an IA-32e Page-Directory Entry that References a Page Table
Bit
Position(s)
Contents
0 (P) Present; must be 1 to reference a page table
1 (R/W) Read/write; if 0, writes may not be allowed to the 2-MByte region controlled by
this entry (depends on CPL and CR0.WP; see Section 4.6)
2 (U/S) User/supervisor; if 0, accesses with CPL=3 are not allowed to the 2-MByte region
controlled by this entry (see Section 4.6)
3 (PWT) Page-level write-through; indirectly determines the memory type used to access
the page table referenced by this entry (see Section 4.9)
4 (PCD) Page-level cache disable; indirectly determines the memory type used to access
the page table referenced by this entry (see Section 4.9)
5 (A) Accessed; indicates whether this entry has been used for linear-address
translation (see Section 4.8)
6Ignored
7 (PS) Page size; must be 0 (otherwise, this entry maps a 2-MByte page; see Table 4-15)
11:8 Ignored
M–1:12 Physical address of 4-KByte aligned page table referenced by this entry
51:M Reserved (must be 0)
62:52 Ignored
63 (XD) If IA32_EFER.NXE = 1, execute-disable (if 1, instruction fetches are not allowed
from the 2-MByte region controlled by this entry; see Section 4.6); otherwise,
reserved (must be 0)