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Vol. 3A xxix
CONTENTS
PAGE
30.10.3 Incrementing the Time-Stamp Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-77
30.10.4 Non-Halted Reference Clockticks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-77
30.10.5 Cycle Counting and Opportunistic Processor Operation . . . . . . . . . . . . . . . . . . . . . . . . . 30-77
30.11 PERFORMANCE MONITORING, BRANCH PROFILING AND SYSTEM EVENTS . . . . . . . . . . 30-78
30.12 PERFORMANCE MONITORING AND DUAL-CORE TECHNOLOGY. . . . . . . . . . . . . . . . . . . . . . 30-79
30.13 PERFORMANCE MONITORING ON 64-BIT INTEL XEON PROCESSOR MP WITH UP TO 8-
MBYTE L3 CACHE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-79
30.14 PERFORMANCE MONITORING ON L3 AND CACHING BUS CONTROLLER SUB-SYSTEMS . 30-
84
30.14.1 Overview of Performance Monitoring with L3/Caching Bus Controller . . . . . . . . . . . 30-86
30.14.2 GBSQ Event Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-87
30.14.3 GSNPQ Event Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-89
30.14.4 FSB Event Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-91
30.14.4.1 FSB Sub-Event Mask Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-92
30.14.5 Common Event Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-93
30.15 PERFORMANCE MONITORING (P6 FAMILY PROCESSOR). . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-93
30.15.1 PerfEvtSel0 and PerfEvtSel1 MSRs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-94
30.15.2 PerfCtr0 and PerfCtr1 MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-96
30.15.3 Starting and Stopping the Performance-Monitoring Counters . . . . . . . . . . . . . . . . . . . 30-96
30.15.4 Event and Time-Stamp Monitoring Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-97
30.15.5 Monitoring Counter Overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-97
30.16 PERFORMANCE MONITORING (PENTIUM PROCESSORS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-98
30.16.1 Control and Event Select Register (CESR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-98
30.16.2 Use of the Performance-Monitoring Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30-100
30.16.3 Events Counted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-100
APPENDIX A
PERFORMANCE-MONITORING EVENTS
A.1 ARCHITECTURAL PERFORMANCE-MONITORING EVENTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
A.2 PERFORMANCE MONITORING EVENTS FOR INTEL
®
CORE
™
I7 PROCESSOR FAMILY. . A-2
A.3 PERFORMANCE MONITORING EVENTS FOR NEXT GENERATION INTEL
®
PROCESSOR
(CODENAMED WESTMERE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-57
A.4 PERFORMANCE MONITORING EVENTS FOR INTEL
®
XEON
®
PROCESSOR 5200, 5400
SERIES AND INTEL
®
CORE
™
2
EXTREME PROCESSORS QX 9000 SERIES . . . . . . . . . . . . A-87
A.5 PERFORMANCE MONITORING EVENTS FOR INTEL
®
XEON
®
PROCESSOR 3000, 3200,
5100, 5300 SERIES AND INTEL
®
CORE
™
2
DUO PROCESSORS. . . . . . . . . . . . . . . . . . . . . . A-88
A.6 PERFORMANCE MONITORING EVENTS FOR INTEL
®
ATOM
™
PROCESSORS. . . . . . . . . A-133
A.7 PERFORMANCE MONITORING EVENTS FOR INTEL
®
CORE
™
SOLO AND INTEL
®
CORE
™
DUO PROCESSORS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-156
A.8 PENTIUM 4 AND INTEL XEON PROCESSOR PERFORMANCE-MONITORING EVENTS. . . A-165
A.9 PERFORMANCE MONITORING EVENTS FOR
INTEL
®
PENTIUM
®
M PROCESSORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-214
A.10 P6 FAMILY PROCESSOR PERFORMANCE-MONITORING EVENTS . . . . . . . . . . . . . . . . . . . . A-217
A.11 PENTIUM PROCESSOR PERFORMANCE-
MONITORING EVENTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-235
APPENDIX B
MODEL-SPECIFIC REGISTERS (MSRS)
B.1 ARCHITECTURAL MSRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2
B.2 MSRS IN THE INTEL
®
CORE
™
2 PROCESSOR FAMILY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-37