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Vol. 3 4-13
PAGING
— Bits 11:0 are from the original linear address.
If a paging-structure entry’s P flag (bit 0) is 0 or if the entry sets any reserved bit, the
entry is used neither to reference another paging-structure entry nor to map a page.
A reference using a linear address whose translation would use such a paging-struc-
ture entry causes a page-fault exception (see Section 4.7).
With 32-bit paging, there are reserved bits only if CR4.PSE = 1:
• If the P flag and the PS flag (bit 7) of a PDE are both 1, the bits reserved depend
on MAXPHYADDR whether the PSE-36 mechanism is supported:
1
— If the PSE-36 mechanism is not supported, bits 21:13 are reserved.
— If the PSE-36 mechanism is supported, bits 21:M–19 are reserved, where M
is the minimum of 40 and MAXPHYADDR.
• If the PAT is not supported:
2
Table 4-5. Format of a 32-Bit Page-Directory Entry that References a Page Table
Bit
Position(s)
Contents
0 (P) Present; must be 1 to reference a page table
1 (R/W) Read/write; if 0, writes may not be allowed to the 4-MByte region controlled by
this entry (depends on CPL and CR0.WP; see Section 4.6)
2 (U/S) User/supervisor; if 0, accesses with CPL=3 are not allowed to the 4-MByte region
controlled by this entry (see Section 4.6)
3 (PWT) Page-level write-through; indirectly determines the memory type used to access
the page table referenced by this entry (see Section 4.9)
4 (PCD) Page-level cache disable; indirectly determines the memory type used to access
the page table referenced by this entry (see Section 4.9)
5 (A) Accessed; indicates whether this entry has been used for linear-address
translation (see Section 4.8)
6Ignored
7 (PS) If CR4.PSE = 1, must be 0 (otherwise, this entry maps a 4-MByte page; see
Table 4-4); otherwise, ignored
11:8 Ignored
31:12 Physical address of 4-KByte aligned page table referenced by this entry
1. See Section 1.1.5 for how to determine MAXPHYADDR and whether the PSE-36 mechanism is
supported.
2. See Section 4.1.4 for how to determine whether the PAT is supported.