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2-24 Vol. 3
SYSTEM ARCHITECTURE OVERVIEW
when set; when clear, processor aliases references to registers DR4 and DR5
for compatibility with software written to run on earlier IA-32 processors.
See also: Section 16.2.2, “Debug Registers DR4 and DR5.”
PSE Page Size Extensions (bit 4 of CR4) — Enables 4-MByte pages with 32-bit
paging when set; restricts 32-bit paging to pages to 4 KBytes when clear.
See also: Section 4.3, “32-Bit Paging.”
PAE Physical Address Extension (bit 5 of CR4) — When set, enables paging
to produce physical addresses with more than 32 bits. When clear, restricts
physical addresses to 32 bits. PAE must be set before entering IA-32e mode.
See also: Chapter 4, “Paging.”
MCE Machine-Check Enable (bit 6 of CR4) — Enables the machine-check
exception when set; disables the machine-check exception when clear.
See also: Chapter 15, “Machine-Check Architecture.”
PGE Page Global Enable (bit 7 of CR4) — (Introduced in the P6 family proces-
sors.) Enables the global page feature when set; disables the global page
feature when clear. The global page feature allows frequently used or shared
pages to be marked as global to all users (done with the global flag, bit 8, in
a page-directory or page-table entry). Global pages are not flushed from the
translation-lookaside buffer (TLB) on a task switch or a write to register CR3.
When enabling the global page feature, paging must be enabled (by setting
the PG flag in control register CR0) before the PGE flag is set. Reversing this
sequence may affect program correctness, and processor performance will
be impacted.
See also: Section 4.10, “Caching Translation Information.”
PCE Performance-Monitoring Counter Enable (bit 8 of CR4) — Enables
execution of the RDPMC instruction for programs or procedures running at
any protection level when set; RDPMC instruction can be executed only at
protection level 0 when clear.
OSFXSR
Operating System Support for FXSAVE and FXRSTOR instructions
(bit 9 of CR4) — When set, this flag: (1) indicates to software that the oper-
ating system supports the use of the FXSAVE and FXRSTOR instructions, (2)
enables the FXSAVE and FXRSTOR instructions to save and restore the
contents of the XMM and MXCSR registers along with the contents of the x87
FPU and MMX registers, and (3) enables the processor to execute
SSE/SSE2/SSE3/SSSE3/SSE4 instructions, with the exception of the PAUSE,
PREFETCHh, SFENCE, LFENCE, MFENCE, MOVNTI, CLFLUSH, CRC32, and
POPCNT.
If this flag is clear, the FXSAVE and FXRSTOR instructions will save and
restore the contents of the x87 FPU and MMX instructions, but they may not
save and restore the contents of the XMM and MXCSR registers. Also, the