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Vol. 3 2-23
SYSTEM ARCHITECTURE OVERVIEW
flag is set, caching of the page-directory is prevented; when the flag is clear,
the page-directory can be cached. This flag affects only the processor’s
internal caches (both L1 and L2, when present). The processor ignores this
flag if paging is not used (the PG flag in register CR0 is clear) or the CD
(cache disable) flag in CR0 is set.
See also: Chapter 11, “Memory Cache Control” (for more about the use of
the PCD flag) and Section 4.9, “Paging and Memory Typing” (for a discussion
of a companion PCD flag in page-directory and page-table entries).
PWT Page-level Write-Through (bit 3 of CR3) — Controls the write-through or
write-back caching policy of the first paging structure of the current paging-
structure hierarchy. When the PWT flag is set, write-through caching is
enabled; when the flag is clear, write-back caching is enabled. This flag
affects only internal caches (both L1 and L2, when present). The processor
ignores this flag if paging is not used (the PG flag in register CR0 is clear) or
the CD (cache disable) flag in CR0 is set.
See also: Section 11.5, “Cache Control” (for more information about the use
of this flag), and Section 4.9, “Paging and Memory Typing” (for a discussion
of a companion PCD flag in the page-directory and page-table entries).
VME Virtual-8086 Mode Extensions (bit 0 of CR4) — Enables interrupt- and
exception-handling extensions in virtual-8086 mode when set; disables the
extensions when clear. Use of the virtual mode extensions can improve the
performance of virtual-8086 applications by eliminating the overhead of
calling the virtual-8086 monitor to handle interrupts and exceptions that
occur while executing an 8086 program and, instead, redirecting the inter
-
rupts and exceptions back to the 8086 program’s handlers. It also provides
hardware support for a virtual interrupt flag (VIF) to improve reliability of
running 8086 programs in multitasking and multiple-processor environ
-
ments.
See also: Section 17.3, “Interrupt and Exception Handling in Virtual-8086
Mode.”
PVI Protected-Mode Virtual Interrupts (bit 1 of CR4) — Enables hardware
support for a virtual interrupt flag (VIF) in protected mode when set; disables
the VIF flag in protected mode when clear.
See also: Section 17.4, “Protected-Mode Virtual Interrupts.”
TSD Time Stamp Disable (bit 2 of CR4) — Restricts the execution of the
RDTSC instruction (including RDTSCP instruction if
CPUID.80000001H:EDX[27] = 1) to procedures running at privilege level 0
when set; allows RDTSC instruction (including RDTSCP instruction if
CPUID.80000001H:EDX[27] = 1) to be executed at any privilege level when
clear.
DE Debugging Extensions (bit 3 of CR4) — References to debug registers
DR4 and DR5 cause an undefined opcode (#UD) exception to be generated