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9-16 Vol. 3
PROCESSOR MANAGEMENT AND INITIALIZATION
9.8.5.3 64-bit Mode and Compatibility Mode Operation
IA-32e mode uses two code segment-descriptor bits (CS.L and CS.D, see Figure 3-8)
to control the operating modes after IA-32e mode is initialized. If CS.L = 1 and CS.D =
0, the processor is running in 64-bit mode. With this encoding, the default operand
size is 32 bits and default address size is 64 bits. Using instruction prefixes, operand
size can be changed to 64 bits or 16 bits; address size can be changed to 32 bits.
When IA-32e mode is active and CS.L = 0, the processor operates in compatibility
mode. In this mode, CS.D controls default operand and address sizes exactly as it
does in the IA-32 architecture. Setting CS.D = 1 specifies default operand and
address size as 32 bits. Clearing CS.D to 0 specifies default operand and address size
as 16 bits (the CS.L = 1, CS.D = 1 bit combination is reserved).
Compatibility mode execution is selected on a code-segment basis. This mode allows
legacy applications to coexist with 64-bit applications running in 64-bit mode. An
operating system running in IA-32e mode can execute existing 16-bit and 32-bit
applications by clearing their code-segment descriptor’s CS.L bit to 0.
In compatibility mode, the following system-level mechanisms continue to operate
using the IA-32e-mode architectural semantics:
• Linear-to-physical address translation uses the 64-bit mode extended page-
translation mechanism.
• Interrupts and exceptions are handled using the 64-bit mode mechanisms.
• System calls (calls through call gates and SYSENTER/SYSEXIT) are handled using
the IA-32e mode mechanisms.
9.8.5.4 Switching Out of IA-32e Mode Operation
To return from IA-32e mode to paged-protected mode operation. Operating systems
must use the following sequence:
1. Switch to compatibility mode.
2. Deactivate IA-32e mode by clearing CR0.PG = 0. This causes the processor to set
IA32_EFER.LMA = 0. The MOV CR0 instruction used to disable paging and
subsequent instructions must be located in an identity-mapped page.
3. Load CR3 with the physical base address of the legacy page-table-directory base
address.
4. Disable IA-32e mode by setting IA32_EFER.LME = 0.
5. Enable legacy paged-protected mode by setting CR0.PG = 1
6. A branch instruction must follow the MOV CR0 that enables paging. Both the MOV
CR0 and the branch instruction must be located in an identity-mapped page.
Registers only available in 64-bit mode (R8-R15 and XMM8-XMM15) are preserved
across transitions from 64-bit mode into compatibility mode then back into 64-bit
mode. However, values of R8-R15 and XMM8-XMM15 are undefined after transitions