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Vol. 3 15-37
MACHINE-CHECK ARCHITECTURE
Table 15-19 lists values of relevant bit fields of IA32_MCi_STATUS for archi-
tecturally defined SRAR errors.
For both the data load and instruction fetch errors, the ADDRV and MISCV
flags in the IA32_MCi_STATUS register are set to indicate that the offending
physical address information is available from the IA32_MCi_MISC and the
IA32_MCi_ADDR registers. For the memory scrubbing and L3 explicit write
-
back errors, the address mode in the IA32_MCi_MISC register should be set
as physical address mode (010b) and the address LSB information in the
IA32_MCi_MISC register should indicate the lowest valid address bit in the
address information provided from the IA32_MCi_ADDR register.
An MCE signal is broadcast to all logical processors on the system on which
the UCR errors are supported. The IA32_MCG_STATUS MSR allows system
software to distinguish the affected logical processor of an SRAR error
amongst logical processors that observed SRAR via a shared MCi_STATUS
bank.
Table 15-20 shows the RIPV and EIPV flag indication in the
IA32_MCG_STATUS register for the data load and instruction fetch errors on
both the reporting and non-reporting logical processors.
The affected logical processor is the one that has detected and raised an
SRAR error at the point of the consumption in the execution flow. The
affected logical processor should find the Data Load or the Instruction Fetch
error information in the IA32_MCi_STATUS register that is reporting the
SRAR error.
For Data Load recoverable errors, the affected logical processor should find
that the IA32_MCG_STATUS.RIPV flag is cleared and the
IA32_MCG_STATUS.EIPV flag is set indicating that the error is detected at
the instruction pointer saved on the stack for this machine check exception
and restarting execution with the interrupted context is not possible.
Table 15-19. IA32_MCi_STATUS Values for SRAR Errors
SRAR Error Valid OVER UC EN MISCV ADDRV PCC S AR MCACOD
Data Load 1 0 1 1 1 1 0 1 1 0x134
Instruction Fetch 1 0 1 1 1 1 0 1 1 0x150
Table 15-20. IA32_MCG_STATUS Flag Indication for SRAR Errors
SRAR Type Affected Logical Processors Non-Affected Logical Processors
RIPV EIPV RIPV EIPV
Data Load 0 1 1 0
instruction Fetch 0 0 1 0