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Vol. 3 10-49
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
lowest priority delivery mode is not supported in cluster mode and must not be
configured by software.
The hierarchical cluster destination model can be used with Pentium 4, Intel
Xeon, P6 family, or Pentium processors. With this model, a hierarchical network
can be created by connecting different flat clusters via independent system or
APIC buses. This scheme requires a cluster manager within each cluster, which is
responsible for handling message passing between system or APIC buses. One
cluster contains up to 4 agents. Thus 15 cluster managers, each with 4 agents,
can form a network of up to 60 APIC agents. Note that hierarchical APIC networks
requires a special cluster manager device, which is not part of the local or the I/O
APIC units.
NOTES
All processors that have their APIC software enabled (using the
spurious vector enable/disable bit) must have their DFRs (Desti-
nation Format Registers) programmed identically.
The default mode for DFR is flat mode. If you are using cluster mode,
DFRs must be programmed before the APIC is software enabled.
Since some chipsets do not accurately track a system view of the
logical mode, program DFRs as soon as possible after starting the
processor.
10.7.2.3 Logical Destination Mode in x2APIC Mode
In x2APIC mode, the Logical Destination Register (LDR) is increased to 32 bits wide.
It is a read-only register to system software. This 32-bit value is referred to as
“logical x2APIC ID”. System software accesses this register via the RDMSR instruc
-
tion reading the MSR at address 80DH. Figure 10-21 provides the layout of the
Logical Destination Register in x2APIC mode.
In the xAPIC mode, the Destination Format Register (DFR) through MMIO interface
determines the choice of a flat logical mode or a clustered logical mode. Flat logical
Figure 10-21. Logical Destination Register in x2APIC Mode
MSR Address: 80DH
31 0
Logical x2APIC ID